3D Vertical IC Inductor Mitigates CMP Dishing
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Solution Overview
Problem
Inductors in integrated circuits face challenges with scaling due to their large footprint and planarization issues caused by chemical-mechanical planarization (CMP) processes, which affect their performance and efficiency.
Innovation Solution
The inductor is oriented with turns arranged along vertical planes intersecting the underlying substrate, utilizing conductive routing layers with alternating conductive wires and vias within dielectric structures, allowing for a larger area without increasing the footprint and mitigating dishing effects from CMP processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If traditional planar inductor configuration is used, then manufacturing process is simple, but footprint area is large and CMP dishing effects occur
Solution Approach 1:
The patent transitions from a traditional planar (2D) inductor configuration to a three-dimensional vertical configuration. The inductor windings are arranged vertically along the z-axis, utilizing multiple conductive layers stacked in the vertical dimension. This dimensional change allows the inductor to achieve high inductance values within a compact footprint area, directly resolving the contradiction between manufacturing simplicity and footprint reduction.
Solution Approach 2:
The patent employs a nested structure where multiple conductive layers are stacked vertically, with each layer containing inductor windings that are nested within the vertical space occupied by other layers. The conductive vias connect these nested layers, forming a compact three-dimensional inductor structure that achieves high inductance in a minimal footprint while maintaining compatibility with standard semiconductor manufacturing processes.
2Ease of manufacture
If traditional planar inductor configuration is used, then manufacturing process is simple, but CMP dishing effects degrade performance
Solution Approach 1:
By moving the inductor windings from a planar configuration to a vertical three-dimensional configuration, the patent eliminates the large planar areas that are susceptible to CMP dishing effects. The vertical arrangement distributes the inductor structure across multiple thin conductive layers, each with small surface area, thereby reducing the impact of CMP-induced non-uniformities on inductor performance while maintaining manufacturing simplicity.
Solution Approach 2:
The patent segments the inductor structure into multiple discrete conductive layers, each containing a portion of the total windings. This segmentation distributes the inductor function across multiple thin layers rather than relying on a single large planar structure, reducing the impact of CMP dishing on any individual layer and improving overall inductor reliability while maintaining ease of manufacture through standard multi-layer fabrication processes.
3Quantity of substance
If inductor area is increased to achieve high inductance, then inductance value improves, but footprint area increases
Solution Approach 1:
The patent achieves high inductance values by utilizing the vertical dimension (z-axis) rather than expanding the planar footprint. Multiple conductive layers are stacked vertically, with each layer contributing to the total number of windings. This three-dimensional arrangement allows the inductor to achieve high inductance (e.g., 100 nH or more) within a compact footprint area, directly resolving the contradiction between inductance value and footprint size.
Solution Approach 2:
The patent employs a nested vertical structure where multiple conductive layers are stacked one above another, with each layer containing inductor windings that are nested within the vertical space. Conductive vias connect these nested layers, forming a compact three-dimensional structure that achieves high inductance values without increasing the planar footprint, as the inductor effectively utilizes the vertical nesting of conductive elements.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enables a high inductance with minimal footprint, meeting design specifications while reducing the impact of CMP-related dishing issues, thus enhancing the performance and density of integrated circuits.
Implementation Method 1
An inductor is a conductive coil having one or more turns, which is configured to store electrical energy in a magnetic field when electric current flows through it
Data Source
AI summary
The present disclosure, in some embodiments, relates to a method of forming an integrated chip. The method may be performed by forming a first conductive wire within a first dielectric structure formed on a first surface of a first substrate. A through-substrate-via (TSV) is formed to extend though the first substrate. A second conductive wire is formed within a second dielectric structure formed on a second surface of the first substrate opposing the first surface. The TSV electrically couples the first conductive wire and the second conductive wire. The first conductive wire, the second conductive wire, and the TSV define an inductor that wraps around an axis.