Vertical IC Package Inductor B-Field Parallel to Substrate
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Solution Overview
Problem
Integrated inductors in IC packages face significant substrate loss due to eddy currents generated by their magnetic fields, which reduces the quality factor and is difficult and costly to mitigate effectively in existing solutions.
Innovation Solution
The implementation of mixed-orientation multi-die IC packages with vertically-mounted dies and integrated inductors where the core magnetic field extends parallel to the substrate major plane, reducing eddy currents and substrate loss by optimizing die orientation and using high resistivity substrates where necessary.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If integrated inductors are implemented in IC packages with conventional substrate mounting, then inductance function is provided, but substrate loss due to eddy currents increases significantly
Solution Approach 1:
The patent applies dimensionality change by mounting the die vertically (in the Z-direction) rather than horizontally (in the XY-plane). This vertical mounting orientation changes the spatial relationship between the inductor's magnetic field and the substrate, causing the magnetic field to extend parallel to the substrate major plane rather than perpendicular to it. This dimensional reorientation reduces eddy current loops in the substrate, thereby reducing substrate loss and improving quality factor.
2Loss of energy
If vertically-mounted dies are used to reduce substrate loss, then eddy current loss decreases, but package complexity increases
Solution Approach 1:
The patent utilizes vertical mounting of dies in the Z-direction, transitioning from conventional planar (XY-plane) packaging to three-dimensional packaging. This approach reduces eddy current loss by orienting the magnetic field parallel to the substrate, while the complexity management is achieved through systematic integration of vertical interconnects and standardized mounting processes.
Solution Approach 2:
The patent implements nested packaging by vertically stacking multiple dies (such as RF die, memory die, logic die) within a single package footprint. This nesting approach allows multiple functional components to be integrated in the vertical dimension, reducing the overall package area while maintaining functionality. The vertical stacking enables efficient use of space with interconnects routing signals between stacked dies.
3Reliability
If conventional horizontal die mounting is used, then package layout is simple, but substrate loss from eddy currents reduces quality factor
Solution Approach 1:
The patent transitions from conventional horizontal die mounting (XY-plane) to vertical die mounting (Z-direction), fundamentally changing the spatial orientation of components. This dimensional change causes the inductor's magnetic field to extend parallel to the substrate major plane, which reduces eddy current loops and substrate loss, thereby improving quality factor. The vertical orientation represents a paradigm shift in package architecture.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces substrate loss and increases the quality factor of integrated inductors, achieving a smaller footprint and lower energy loss while maintaining performance and cost-effectiveness.
Implementation Method 1
integrated inductors where the core magnetic field extends parallel to the substrate major plane
Implementation Method 2
substrate loss due to eddy currents generated by their magnetic fields
Data Source
AI summary
An integrated circuit (IC) package product, e.g., system-on-chip (SoC) or system-in-package (SiP) product, may include at least one integrated inductor having a core magnetic field (B field) that extends parallel to the substrate major plane of at least one die or chiplet included in or mounted to the product, which may reduce the eddy currents within each die/chiplet substrate, and thereby reduce energy loss of the indictor. The IC package product may include a horizontally-extending IC package substrate, a horizontally-extending die mount base arranged on the IC package substrate, at least one die mounted to the die mount base in a vertical orientation, and an integrated inductor having a B field extending in a vertical direction parallel to the silicon substrate of each vertically-mounted die, thereby providing a reduced substrate loss in the integrated inductor, which provides an increased quality factor (Q) of the inductor.