Vertical Inductors with Interconnected Parts for High Density
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Solution Overview
Problem
Achieving high inductance values in integrated circuits is challenging due to the limitations of three-dimensional inductors, including smaller distances between metal layers, the need for dummy patterns, and undesirable Eddy currents in semiconductor substrates, which restrict the improvement of inductance density.
Innovation Solution
The development of vertical helical inductors formed in multiple metal layers with interconnected parts, where metal lines and vias create spiral metal features extending in vertical planes, allowing for increased inductance density without significant increases in chip area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If three-dimensional inductors are formed in multiple metal layers to improve inductance, then inductance density is improved, but the distance between metal layers and substrate becomes smaller causing Eddy currents and limiting further improvement
Solution Approach 1:
The patent transitions from conventional planar spiral inductors to vertical inductors that extend in the vertical dimension perpendicular to the substrate surface. This dimensional change allows the inductor to achieve high inductance density without requiring metal layers to be positioned close to the substrate, thereby avoiding Eddy current losses while maintaining compact footprint.
Solution Approach 2:
The vertical inductor is divided into multiple segments or parts formed in different metal layers, where each segment contributes to the overall inductance. The inductor comprises multiple parts with each part extending in vertical planes, and these parts are interconnected through conductive vias, allowing the inductance to be distributed across multiple layers without requiring close spacing.
2Quantity of substance
If conventional spiral inductors are used to achieve high inductance, then inductance value is improved, but chip area usage increases significantly
Solution Approach 1:
The patent employs vertical inductors that extend perpendicular to the substrate surface, utilizing the vertical dimension to achieve high inductance values. This approach concentrates the inductance-generating structure in the vertical direction rather than spreading it out in the planar direction, thereby achieving high inductance with minimal chip area occupation.
Solution Approach 2:
The vertical inductor structure nests multiple conductive parts and interconnecting vias within a compact vertical space above a small footprint area on the substrate. The multiple parts are stacked vertically and interconnected, creating a nested configuration that maximizes inductance within a minimal horizontal area.
3Area of stationary object
If metal layers are positioned closer to substrate to reduce chip area, then area efficiency is improved, but Eddy currents increase and inductance improvement is limited
Solution Approach 1:
The patent positions the inductor structure in the vertical dimension away from the substrate surface, using multiple metal layers stacked vertically at distances that avoid substrate proximity effects. This vertical positioning maintains area efficiency while preventing Eddy current losses by keeping the inductor structure sufficiently distant from the conductive substrate.
Solution Approach 2:
The patent introduces dielectric layers and insulating structures as intermediaries between the vertical inductor parts and the substrate. These intermediary layers provide electrical isolation and prevent direct coupling between the inductor and substrate, thereby eliminating Eddy current paths while maintaining the compact vertical structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enhances inductance density and quality factor (Q value), enabling high-frequency applications with improved performance compared to conventional spiral inductors, while maintaining a compact footprint.
Implementation Method 1
A vertical inductor is provided. The vertical inductor includes a plurality of parts formed of metal, wherein each of the parts extends in one of a plurality of planes perpendicular to a major surface of the substrate. Metal lines interconnect neighboring ones of the plurality of parts of the vertical inductor.
Data Source
AI summary
A device includes a substrate, and a vertical inductor over the substrate. The vertical inductor includes a plurality of parts formed of metal, wherein each of the parts extends in one of a plurality of planes perpendicular to a major surface of the substrate. Metal lines interconnect neighboring ones of the plurality of parts of the vertical inductor.