Vertical Interconnect Capacitor Fabrication via Substrate Oxidation
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Solution Overview
Problem
Conventional methods for fabricating interconnect capacitors in semiconductor technology require substantial silicon area to achieve high capacitance values, limiting the efficiency of chip interconnects and increasing manufacturing costs.
Innovation Solution
A method involving the formation of vertical conductors between chips, where a substrate with openings is oxidized to create insulation layers and filled with conductive material, allowing for the creation of a vertical capacitor structure that maximizes capacitance while minimizing silicon area usage, and can be integrated with existing processes to simplify manufacturing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional MIM capacitor fabrication is used, then capacitor structure is formed, but substantial silicon area is required for large capacitance values
Solution Approach 1:
The patent transitions from planar MIM capacitor structure to vertical capacitor structure by utilizing the depth dimension of the substrate. Capacitor electrodes are formed as vertical columns extending through the substrate thickness, with insulation layers deposited on the sidewalls. This vertical configuration increases the effective capacitance area without consuming additional planar silicon area, directly resolving the contradiction between achieving high capacitance values and minimizing silicon area usage.
2Manufacturing precision
If multiple separate processes are used for forming vias and capacitors, then precise structure is achieved, but process complexity increases
Solution Approach 1:
The patent combines the formation of interconnection vias and capacitor structures into a single integrated process. Both types of structures are formed simultaneously through one etching process that creates openings for both purposes. The insulation layers are then deposited uniformly on all sidewalls, and conductive materials are filled in a unified sequence. This merging approach maintains manufacturing precision while significantly reducing process complexity and the number of fabrication steps required.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the creation of high-capacitance interconnect capacitors with significant silicon area savings, reducing manufacturing costs and process complexity by forming both interconnection vias and capacitors in a single etching process.
Implementation Method 1
submitting the substrate including the openings to an oxidation process to form an oxide layer covering the sidewalls and the bottom of the openings
Implementation Method 2
depositing a conductive material layer over the oxide layer in the openings such that the conductive material layer is electrically continuous
Data Source
AI summary
A method for fabricating a capacitor includes providing a substrate having a first surface and a second surface, and forming a plurality of openings in the substrate, the openings are separated from each other by a shape of the substrate, each opening having sidewalls and a bottom. The method further includes submitting the substrate including the openings to an oxidation process to form an oxide layer covering the sidewalls and the bottom of the openings, and a portion of a surface of the substrate, wherein a shape of the substrate disposed between a pair of two adjacent openings is completely oxidized to form an insulation layer between the pair of two adjacent openings; and depositing a conductive material layer over the oxide layer in the openings such that the conductive material layer is electrically continuous and such that the pair of adjacent openings form a capacitor.