Vertical Interconnect Packaging With Redistribution Fan-Out
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Solution Overview
Problem
Conventional electronic packages and manufacturing methods result in excessive costs, decreased reliability, and large package sizes, leading to suboptimal performance.
Innovation Solution
The proposed solution involves a semiconductor device structure comprising a base substrate with vertical interconnects and a redistribution structure, where the substrate encapsulant exposes the distal ends of the interconnects, and a redistribution structure with conductive and dielectric layers that fan out electrical connections, allowing for efficient integration of electronic components.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional electronic packages and manufacturing methods are used, then manufacturing simplicity is maintained, but package size becomes too large, cost increases, and reliability decreases
Solution Approach 1:
The patent transitions from planar interconnect layouts to three-dimensional vertical interconnect structures. Multiple interconnect levels are stacked vertically with redistribution layers connecting different levels, enabling compact packaging while maintaining signal integrity and reducing package footprint.
Solution Approach 2:
The patent implements nested interconnect structures where lower-level interconnects are positioned beneath upper-level interconnects in a vertical stack. This nesting arrangement allows multiple connection paths to occupy overlapping horizontal spaces, reducing overall package size while maintaining electrical connectivity.
2Productivity
If conventional package structures are used, then manufacturing complexity is low, but performance is suboptimal due to large package size
Solution Approach 1:
The patent divides the interconnect structure into discrete segments including vertical interconnects, redistribution layers, and connection terminals. Each segment performs a specific function and can be independently optimized, allowing high-performance designs while managing manufacturing complexity through modular construction.
Solution Approach 2:
The patent utilizes vertical stacking to achieve high-density interconnections without increasing horizontal package dimensions. Multiple signal paths are routed through different vertical levels, enabling enhanced performance through increased interconnect capacity while maintaining compact form factor.
3Manufacturing precision
If conventional interconnect methods are used, then manufacturing process is simple, but interconnect pitch is coarse and performance is limited
Solution Approach 1:
The patent achieves fine pitch interconnects by transitioning to vertical routing rather than planar routing. Multiple thin vertical interconnects can be closely spaced in the vertical dimension, enabling finer pitch without the manufacturing challenges associated with dense planar traces.
Solution Approach 2:
The patent employs nested interconnect levels where finer-pitch upper-level interconnects are positioned above coarser lower-level interconnects. This nesting enables progressive pitch reduction through multiple levels, achieving high precision interconnections while managing overall structural complexity.
Data Source
AI summary
In one example, an electronic device includes a substrate including a substrate upper side and a conductive structure comprising substrate upper terminals adjacent to the substrate upper side. Vertical interconnects are coupled to the substrate upper terminals. An encapsulant covers portions of the substrate and the vertical interconnects. The vertical interconnects are exposed from an upper side of the encapsulant. A redistribution structure is over the encapsulant and includes a redistribution structure upper side, a redistribution structure lower side, a redistribution dielectric structure, and a redistribution conductive structure. The redistribution structure includes redistribution upper terminals adjacent to the redistribution structure upper side and redistribution bottom terminals adjacent to the redistribution lower side. The redistribution bottom terminals are coupled to the vertical interconnects and the redistribution upper terminals. An electronic component is coupled to the redistribution upper terminals. Other examples and related methods are also disclosed herein.