Vertical Interconnect Structure for IPD Heat Dissipation
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Solution Overview
Problem
Semiconductor devices face challenges in achieving high-quality integrated passive devices (IPDs) with enhanced interconnect capability, heat dissipation, and reduced package size, particularly in high-frequency applications where electromagnetic interference and thermal expansion issues are prevalent.
Innovation Solution
A semiconductor device with a substrate featuring conductive vias and a vertical interconnect structure that separates IPDs from baseband circuits using a high-resistivity encapsulant, allowing for efficient electrical connections and heat dissipation while minimizing package size and silicon area consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If IPDs are formed side-by-side on the same wafer level, then interconnect capability is improved, but silicon area consumption increases
Solution Approach 1:
The patent transitions from a planar side-by-side arrangement of IPDs on the same wafer level to a vertical stacked arrangement across multiple wafer levels. This dimensional change allows multiple IPDs to be interconnected through vertical vias and interconnect structures, achieving enhanced interconnect capability while reducing the lateral silicon area footprint.
2Object-affected harmful factors
If high-resistivity substrate is used for IPDs, then electromagnetic interference is reduced, but package size increases
Solution Approach 1:
The patent employs a vertical stacked architecture where high-resistivity substrate regions are utilized selectively for specific IPDs at different vertical levels. The vertical interconnect structures (vias and through-silicon vias) enable electrical connections between stacked IPDs while confining the high-resistivity material to only the necessary regions, thereby reducing EMI without proportionally increasing the overall package footprint.
Solution Approach 2:
The patent divides the substrate into multiple functional regions with different resistivity characteristics. High-resistivity regions are segmented and placed specifically where EMI shielding is needed for RF IPDs, while lower-resistivity regions are used for baseband circuits and interconnect structures. This segmentation allows EMI reduction in critical areas without requiring the entire package to use high-resistivity material, thus controlling package size.
3Temperature
If vertical interconnect structure is formed, then heat dissipation is improved, but manufacturing complexity increases
Solution Approach 1:
The patent implements vertical heat dissipation pathways through the stacked architecture. Thermal vias and through-silicon vias provide direct vertical thermal conduction paths from upper IPD layers down to the substrate and package bottom, enabling efficient heat removal. This vertical thermal management approach leverages the same vertical interconnect infrastructure, achieving improved heat dissipation without adding separate complex thermal management systems.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables improved interconnect capability, effective heat dissipation, and a smaller package size, reducing electromagnetic interference and thermal expansion issues, thereby enhancing the performance and reliability of semiconductor devices in high-frequency applications.
Implementation Method 1
high frequency electrical devices generate or are susceptible to undesired electromagnetic interference (EMI) and radio frequency interference (RFI)
Implementation Method 2
A plurality of vertical conductive structures is formed through the encapsulant between the IPD structure and first interconnect structure
Implementation Method 3
A second interconnect structure is formed over a surface of the substrate opposite the IPD structure and electrically connected to the conductive vias
Data Source
AI summary
A semiconductor device is made with a conductive via formed through a top-side of the substrate. The conductive via extends vertically through less than a thickness of the substrate. An integrated passive device (IPD) is formed over the substrate. A plurality of first conductive pillars is formed over the first IPD. A first semiconductor die is mounted over the substrate. An encapsulant is formed around the first conductive pillars and first semiconductor die. A second IPD is formed over the encapsulant. An interconnect structure is formed over the second IPD. The interconnect structure operates as a heat sink. A portion of a back-side of the substrate is removed to expose the first conductive via. A second semiconductor die is mounted to the back-side of the substrate. The second semiconductor die is electrically connected to the first IPD and first semiconductor die through the conductive via.