Vertically Spaced Interconnect Lines for Lower RC Delay
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Solution Overview
Problem
The increasing density of interconnect metallization structures in integrated circuits leads to higher resistance-capacitance (RC) delay, which is not effectively addressed by traditional methods of increasing line width, as it reduces line density.
Innovation Solution
Implementing vertically spaced intra-level metallization lines with self-aligned fabrication processes, where upper and lower metallization lines are vertically separated and fabricated from a single pattern, allowing for increased line width without reducing density, and using dielectric materials to isolate and interconnect these lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If line width is increased to reduce resistance, then electrical resistance decreases, but line density reduces
Solution Approach 1:
The patent introduces a vertical dimension to the traditionally planar interconnect structure by forming upper and lower metallization lines at different heights within the same interconnect level. This vertical stacking allows multiple conductive paths to occupy the same lateral footprint, effectively increasing line density while maintaining adequate line width for low resistance. The vertical separation enables independent routing of signals that would otherwise require lateral spacing.
2Reliability
If line width is increased to reduce RC delay, then resistance decreases, but the number of lines per unit area decreases
Solution Approach 1:
By utilizing the vertical dimension through multi-layer metallization structures, the patent achieves multiple conductive pathways within the same planar area. This allows the circuit design to use wider individual lines for lower resistance without sacrificing the overall number of interconnect lines that can be packed into a given area, thus reducing RC delay while maintaining high interconnect capacity.
Solution Approach 2:
The patent implements a nested arrangement where upper and lower metallization lines are vertically stacked within the same lateral footprint. This nesting allows the interconnect structure to contain multiple conductive elements (upper line, lower line) within a single planar location, effectively multiplying the interconnect capacity per unit area while each individual line maintains sufficient width for low resistance.
3Quantity of substance
If vertically spaced metallization lines are implemented to maintain density with wider lines, then manufacturing complexity increases
Solution Approach 1:
The patent employs preliminary patterning actions where mandrel structures and spacer layers are formed in advance to define the positions of upper and lower metallization lines. These preliminary structures serve as templates that guide subsequent deposition and etching processes, ensuring precise vertical alignment and spacing without requiring complex real-time control during metallization formation.
Solution Approach 2:
The patent introduces intermediary structures such as spacer layers and mandrels that mediate the formation of vertically spaced metallization lines. These intermediary elements simplify the manufacturing process by providing self-aligned references for subsequent steps, reducing the need for complex alignment procedures and making the multi-layer structure more manufacturable.
Data Source
AI summary
An integrated circuit interconnect level including a lower metallization line vertically spaced from upper metallization lines. Lower metallization lines may be self-aligned to upper metallization lines enabling increased metallization line width without sacrificing line density for a given interconnect level. Combinations of upper and lower metallization lines within an interconnect metallization level may be designed to control intra-layer resistance/capacitance of integrated circuit interconnect. Dielectric material between two adjacent co-planar metallization lines may be recessed or deposited selectively to the metallization lines. Supplemental metallization may then be deposited and planarized. A top surface of the supplemental metallization may either be recessed to form lower metallization lines between upper metallization lines, or planarized with dielectric material to form upper metallization lines between lower metallization lines. Vias to upper and lower metallization line may extend another metallization level.