Vertical Interconnect Gap-Fill for Low-Resistance Contacts
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Solution Overview
Problem
The semiconductor industry faces challenges in reducing parasitic resistance and capacitance while increasing the density of interconnect features in integrated circuits, particularly in forming small-diameter, high-aspect-ratio vertical conductive contacts with low contact resistance.
Innovation Solution
The use of multi-step gap-fill techniques and the elimination of conductive liners in forming vertical conductive structures within insulating layers to create low-resistance contacts, allowing for efficient electrical connections between gate electrodes and interconnect structures without the increased resistance associated with conductive liners.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conductive liners are used in vertical conductive structures, then adhesion and filling are improved, but parasitic resistance increases
Solution Approach 1:
The patent removes the conductive liner layer from the vertical conductive structure, extracting the harmful element (parasitic resistance) while maintaining the essential function of electrical connection. The liner is completely eliminated rather than modified, achieving lower resistance paths.
Solution Approach 2:
The patent changes the material composition parameter by replacing the conductive liner material with a direct metal-fill approach or alternative adhesion strategy, fundamentally altering the resistance characteristic of the vertical interconnect structure.
2Quantity of substance
If feature sizes are reduced to increase density, then packing density improves, but manufacturing precision requirements increase
Solution Approach 1:
The patent performs preliminary gap-fill deposition before final patterning, ensuring that material is pre-positioned in the correct locations at larger dimensions where manufacturing precision is more achievable, then subsequent steps refine the final small-diameter features.
Solution Approach 2:
The patent transitions from planar patterning to vertical gap-fill approaches, utilizing the vertical dimension for material deposition and then using lateral etching or planarization to define the final horizontal features, effectively moving the precision-critical step to a different dimensional regime.
3Quantity of substance
If multiple patterning is used to reduce minimum feature size, then interconnect density increases, but device complexity increases
Solution Approach 1:
The patent combines multiple patterning operations into a unified gap-fill process where material is deposited to simultaneously define multiple interconnect features in a single step, merging sequential operations into a parallel process.
Solution Approach 2:
The gap-fill process is self-aligning and self-defining, where the deposited material automatically conforms to the underlying topography and defines the final feature geometry without requiring additional alignment steps or complex patterning operations.
Data Source
AI summary
Vertical interconnect structures and methods of forming are provided. The vertical interconnect structures may be formed by partially filling a first opening through one or more dielectric layers with layers of conductive materials. A second opening is formed in a dielectric layer such that a depth of the first opening after partially filling with the layers of conductive materials is close to a depth of the second opening. The remaining portion of the first opening and the second opening may then be simultaneously filled.