Vertical Interconnect Structure for Low-Cost PoP Packaging
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Solution Overview
Problem
Conventional methods for forming vertical interconnects in 3D wafer-level semiconductor packages, such as through silicon vias (TSV) and through mold vias (TMV), require costly laser drilling or etching processes, increasing manufacturing costs and complexity.
Innovation Solution
A method for forming vertical interconnect structures without etching, drilling, or laser direct ablation (LDA) by using ultraviolet light to pattern photoresist layers and fill the formed vias with conductive material, eliminating the need for specialized equipment and additional processing steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If laser drilling or etching process is used to form vias, then vertical interconnect structures can be formed, but manufacturing costs increase and process complexity increases
Solution Approach 1:
The patent replaces mechanical laser drilling or chemical etching processes with a photoresist-based patterning method. UV light is used to pattern the photoresist layer, forming vias through photolithography rather than mechanical or chemical removal of material. This substitution eliminates the need for expensive laser drilling equipment and complex etching processes while maintaining via formation precision.
Solution Approach 2:
The invention changes the fundamental parameter of via formation from material removal (etching/drilling) to material deposition and patterning (photoresist-based method). By using UV light to pattern photoresist and then filling the patterned areas with conductive material, the process transforms the via formation mechanism, reducing manufacturing complexity and cost while preserving precision.
2Manufacturing precision
If laser drilling or etching process is used to form vias, then vertical interconnect structures can be formed, but device complexity increases
Solution Approach 1:
The patent merges the via formation process with the existing photolithography workflow used in semiconductor manufacturing. By using UV light to pattern photoresist in the same manner as other lithographic steps, the via formation is integrated into the standard fabrication process flow, eliminating the need for separate, specialized laser drilling or etching equipment and reducing overall process complexity.
Solution Approach 2:
The replacement of mechanical/chemical etching with optical patterning using UV light and photoresist simplifies the device fabrication process. The photoresist-based method uses standard photolithography equipment already present in semiconductor factories, reducing the number of additional specialized steps required compared to laser drilling or etching processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces manufacturing costs and simplifies the process by eliminating the need for expensive etching or drilling, while maintaining the integrity of the semiconductor device interconnects, thereby enhancing the efficiency and cost-effectiveness of semiconductor package production.
Implementation Method 1
A method for forming vertical interconnect structures without etching, drilling, or laser direct ablation (LDA) by using ultraviolet light to pattern photoresist layers
Data Source
AI summary
A semiconductor device has a substrate and a first light sensitive material formed over the substrate. A plurality of first conductive posts is formed over the substrate by patterning the first light sensitive material and filling the pattern with a conductive material. A plurality of electrical contacts is formed over the substrate and the conductive posts are formed over the electrical contacts. A first electric component is disposed over the substrate between the first conductive posts. A plurality of second conductive posts is formed over the first electrical component by patterning a second light sensitive material and filling the pattern with conductive material. A first encapsulant is deposited over the first electrical component and conductive posts. A portion of the first encapsulant is removed to expose the first conductive posts. A second electrical component is disposed over the first electrical component and covered with a second encapsulant.