Vertical Interconnect Posts for POP Modules Without Via Drilling
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional via formation in semiconductor devices, such as through silicon vias (TSV) and through mold vias (TMV), involves costly laser drilling or etching processes, increasing manufacturing costs due to specialized equipment and additional steps.
Innovation Solution
Formation of vertical interconnect structures without etching, drilling, or laser direct ablation (LDA) by using photoresist patterning and metal deposition processes to create conductive posts, followed by encapsulation and singulation, reducing the need for costly etching and drilling steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If laser drilling or etching processes are used to form via holes, then vertical electrical interconnects can be achieved, but manufacturing costs increase due to specialized equipment and additional process steps
Solution Approach 1:
The patent extracts and eliminates the costly laser drilling and etching steps from the manufacturing process. Instead of using specialized equipment to create via holes, the invention uses a photoresist-based planarization process that forms conductive posts directly, removing the need for expensive via formation equipment and reducing process complexity while maintaining reliable vertical electrical interconnects
Solution Approach 2:
The patent replaces the mechanical/thermal laser drilling and plasma etching systems with a photochemical process. The photoresist pattern is formed using UV light exposure and chemical development, substituting costly mechanical/thermal field systems with optical and chemical fields, thereby reducing equipment costs and process complexity
2Reliability
If laser drilling or etching processes are used to form via holes, then vertical electrical interconnects can be achieved, but process complexity increases due to additional manufacturing steps
Solution Approach 1:
The patent merges the via hole formation and conductive material deposition into a single integrated process step. The photoresist pattern acts as both the via definition and the conductive fill template, eliminating the need for separate via drilling/etching and metal deposition steps, thereby reducing process complexity while ensuring reliable electrical interconnects
Solution Approach 2:
The photoresist pattern serves multiple functions simultaneously: it defines the via hole location, acts as the conductive material template, and provides the structural framework for the vertical interconnect. This multi-functionality eliminates the need for separate process steps for each function, reducing overall process complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Reduces manufacturing costs and complexity by eliminating the need for specialized etching and drilling equipment, while maintaining effective electrical interconnects, thereby enhancing the efficiency and cost-effectiveness of semiconductor device production.
Implementation Method 1
A photoresist layer is formed over the encapsulant and exposed to UV light through a photomask
Implementation Method 2
Metal deposition processes to create conductive posts
Data Source
AI summary
A semiconductor device has a substrate and a first light sensitive material formed over the substrate. A plurality of first conductive posts is formed over the substrate by patterning the first light sensitive material and filling the pattern with a conductive material. A plurality of electrical contacts is formed over the substrate and the conductive posts are formed over the electrical contacts. A first electric component is disposed over the substrate between the first conductive posts. A plurality of second conductive posts is formed over the first electrical component by patterning a second light sensitive material and filling the pattern with conductive material. A first encapsulant is deposited over the first electrical component and conductive posts. A portion of the first encapsulant is removed to expose the first conductive posts. A second electrical component is disposed over the first electrical component and covered with a second encapsulant.