Vertically Spaced Interconnect Metallization for Lower RC Delay
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Solution Overview
Problem
As integrated circuit (IC) density increases, interconnect parasitics such as resistance-capacitance (RC) delay become a significant challenge due to the density of interconnect metallization structures, and existing techniques struggle to maintain line density while reducing interconnect resistance by increasing line width.
Innovation Solution
The method involves vertically spacing intra-level metallization lines within an interconnect metallization level, allowing for self-aligned fabrication and increased line fill factor, which reduces electrical resistance and parasitic capacitance while maintaining high line density, by recessing dielectric material between lines and depositing metallization in a way that the lower lines occupy the space between upper lines without lateral separation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If line width is increased to reduce interconnect resistance, then resistance decreases, but line density within a given interconnect metallization level decreases
Solution Approach 1:
The patent transitions from a two-dimensional planar arrangement of metallization lines to a three-dimensional vertically spaced arrangement. By spacing lines vertically at different heights within the same interconnect level, the structure achieves increased effective line width and fill factor without reducing the number of lines per unit area, thus reducing resistance while maintaining line density.
Solution Approach 2:
The patent nests multiple metallization lines at different vertical levels within the same horizontal footprint. Lower metallization lines are positioned beneath upper metallization lines, allowing both to occupy the same lateral space without lateral separation, effectively nesting one set of lines within the vertical space of another set.
2Productivity
If IC density increases to improve performance, then performance improves, but interconnect parasitics such as RC delay increase
Solution Approach 1:
By utilizing the vertical dimension to space metallization lines at different heights, the patent reduces parasitic capacitance between adjacent lines while maintaining high IC density. The vertical separation decreases the overlapping area between electric fields of adjacent lines, thereby reducing capacitive coupling and RC delay.
Solution Approach 2:
The patent segments the interconnect level into multiple vertically spaced planes, with first metallization lines at an upper plane and second metallization lines at a lower plane. This segmentation allows independent optimization of each plane's line routing and spacing, reducing overall parasitic effects while maintaining high density.
Data Source
Figure 1
Figure 2A~2B
Figure 3A~3B
AI summary
An integrated circuit interconnect level including a lower metallization line vertically spaced from upper metallization lines. Lower metallization lines may be self-aligned to upper metallization lines enabling increased metallization line width without sacrificing line density for a given interconnect level. Combinations of upper and lower metallization lines within an interconnect metallization level may be designed to control intra-layer resistance/capacitance of integrated circuit interconnect. Dielectric material between two adjacent co-planar metallization lines may be recessed or deposited selectively to the metallization lines. Supplemental metallization may then be deposited and planarized. A top surface of the supplemental metallization may either be recessed to form lower metallization lines between upper metallization lines, or planarized with dielectric material to form upper metallization lines between lower metallization lines. Vias to upper and lower metallization line may extend another metallization level.