Vertical Interconnect Structure for 3D FO-WLCSP
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current methods for forming vertical electrical interconnections in 3-D fan-out wafer level chip scale packages (FO-WLCSPs) are slow, costly, and prone to defects due to the use of conductive through silicon vias (TSVs) and through hole vias (THVs), which require electroplating and result in voids and reliability issues.
Innovation Solution
A method involving the formation of a semiconductor device with a vertical interconnect structure that includes forming an insulating layer around a semiconductor die, followed by a conductive layer and a series of openings and interconnect structures, such as conductive pillars and bumps, to create efficient electrical connections without the need for TSVs or THVs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conductive through silicon vias (TSVs) and through hole vias (THVs) are used to form vertical electrical interconnections, then electrical connectivity between semiconductor dies is achieved, but manufacturing time increases and production costs rise
Solution Approach 1:
The patent extracts and eliminates the TSV/THV formation process from the interconnection methodology. Instead of forming vertical vias through silicon substrates requiring electroplating, the invention uses direct bonding techniques with conductive paste or metallization layers applied to die surfaces, thereby removing the time-consuming via formation steps while maintaining electrical connectivity
Solution Approach 2:
The patent segments the interconnection process into separate die bonding operations rather than requiring through-substrate vias. Each die is independently prepared with conductive elements and bonded to adjacent dies, allowing parallel processing and eliminating the sequential via formation steps that constrain productivity
2Reliability
If electroplating is used to form conductive TSVs and THVs, then vertical electrical interconnections are created, but manufacturing costs increase
Solution Approach 1:
The patent replaces expensive electroplating processes with cheaper alternative materials such as conductive paste, screen-printed metallization, or evaporated metal layers. These materials achieve sufficient electrical conductivity for interdie connections without requiring the costly electroplating equipment and materials, thereby reducing manufacturing costs while maintaining functional reliability
3Reliability
If electroplating is used to form TSVs and THVs, then conductive interconnections are created, but voids form and reliability decreases
Solution Approach 1:
The patent removes the electroplating step entirely from the interconnection process. By using direct deposition methods such as screen printing, paste application, or physical vapor deposition, the process eliminates the void formation problem inherent in electroplating where air bubbles or incomplete filling create reliability issues in vertical vias
Solution Approach 2:
Instead of forming conductive paths from the top down through electroplating in pre-drilled vias, the patent inverts the approach by applying conductive materials directly to die surfaces and bonding dies together, allowing the conductive material to be deposited as a continuous layer without the void formation problems of via filling
Data Source
AI summary
A semiconductor device has a temporary carrier. A semiconductor die is oriented with an active surface toward, and mounted to, the temporary carrier. An encapsulant is deposited with a first surface over the temporary carrier and a second surface, opposite the first surface, is deposited over a backside of the semiconductor die. The temporary carrier is removed. A portion of the encapsulant in a periphery of the semiconductor die is removed to form an opening in the first surface of the encapsulant. An interconnect structure is formed over the active surface of the semiconductor die and extends into the opening in the encapsulant layer. A via is formed and extends from the second surface of the encapsulant to the opening. A first bump is formed in the via and electrically connects to the interconnect structure.