Vertical Interconnect Structure for 3-D FO-WLCSP
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Solution Overview
Problem
Conventional three-dimensional (3-D) fan-out wafer level chip scale packages (FO-WLCSPs face challenges in forming efficient and cost-effective vertical electrical interconnections due to the complexity and cost of forming redistribution layers (RDLs) and conductive interconnect structures, which can lead to defects and warpage issues.
Innovation Solution
A vertical interconnect structure is developed using conductive pillars and encapsulants to provide electrical connectivity between semiconductor dies and external devices, reducing the need for multiple RDLs and improving mechanical support, while also simplifying the manufacturing process by using a combination of deposition and patterning techniques to form conductive layers and insulation layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional redistribution layers (RDLs) and conductive interconnect structures are used for vertical electrical interconnections, then electrical connectivity between semiconductor dies and external devices is achieved, but the manufacturing complexity and cost increase significantly
Solution Approach 1:
The patent transitions from planar RDL interconnect architecture to vertical through-silicon via (TSV) interconnect architecture. This dimensional change enables electrical connectivity through the thickness of the semiconductor substrate, eliminating the need for complex multi-layer RDL structures and reducing manufacturing complexity while maintaining reliable electrical connections between stacked dies and external devices.
Solution Approach 2:
The patent extracts and removes the complex RDL structure from the interconnect architecture, replacing it with simpler vertical TSV structures. By taking out the unnecessary RDL layers and using direct vertical through-silicon vias filled with conductive material, the manufacturing process is simplified while electrical connectivity is maintained through the substrate.
2Reliability
If conventional RDLs and conductive interconnect structures are formed, then electrical interconnection is established, but fabrication costs increase
Solution Approach 1:
The patent employs vertical TSV interconnects that pass through the substrate thickness, replacing expensive multi-layer RDL fabrication processes. This dimensional approach reduces the number of deposition and patterning cycles required, directly lowering fabrication costs while ensuring reliable electrical interconnection through the simplified vertical path.
Solution Approach 2:
The patent uses temporary sacrificial layers during TSV formation that are later removed, replacing the need for expensive permanent RDL structures. The sacrificial layers serve their purpose during manufacturing and are then discarded, providing a cost-effective pathway to achieve reliable electrical interconnection without the high costs associated with conventional RDL fabrication.
3Reliability
If multiple RDLs and conductive interconnect structures are used, then vertical electrical interconnection is achieved, but warpage and defects occur
Solution Approach 1:
The patent removes the multiple RDL layers that cause warpage and manufacturing defects, replacing them with direct vertical TSV interconnects. By extracting the problematic multi-layer RDL structure and using simpler through-silicon via formation with conductive filling, the patent achieves reliable vertical electrical interconnection while minimizing warpage and defects.
Solution Approach 2:
The patent uses composite material structures in the TSV formation process, including sacrificial layers, barrier layers, and conductive fill materials. These composite structures enable precise control during manufacturing, reducing warpage and defects while achieving reliable vertical electrical interconnection through the substrate.
Data Source
AI summary
A semiconductor device has an encapsulant deposited over a first surface of the semiconductor die and around the semiconductor die. A first insulating layer is formed over a second surface of the semiconductor die opposite the first surface. A conductive layer is formed over the first insulating layer. An interconnect structure is formed through the encapsulant outside a footprint of the semiconductor die and electrically connected to the conductive layer. The first insulating layer includes an optically transparent or translucent material. The semiconductor die includes a sensor configured to receive an external stimulus passing through the first insulating layer. A second insulating layer is formed over the first surface of the semiconductor die. A conductive via is formed through the first insulating layer outside a footprint of the semiconductor die. A plurality of stacked semiconductor devices is electrically connected through the interconnect structure.