Vertical Interconnect Stud Bumps in Fan-Out Packages
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Solution Overview
Problem
Current methods for forming vertical electrical interconnections in semiconductor packages, such as through silicon vias (TSVs) or through hole vias (THVs), are time-consuming, costly, and prone to defects like voids and cracking, which affect the reliability and yield of semiconductor devices.
Innovation Solution
A method involving the formation of vertical interconnect structures using stud bumps and integrated passive devices (IPDs) within fan-out wafer level chip scale packages (FO-WLCSP), where a conductive layer is formed outside the semiconductor die, followed by the deposition of an encapsulant and the creation of interconnect structures on both surfaces, including IPDs connected to stud bumps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If through silicon vias (TSVs) or through hole vias (THVs) are used for vertical electrical interconnections, then electrical connectivity is achieved, but manufacturing time increases and costs rise
Solution Approach 1:
The patent extracts the interconnect function from traditional through-silicon via structures and relocates it to the encapsulant material itself. Conductive particles are embedded within the encapsulant to create conductive pathways, eliminating the need for complex via formation processes while maintaining electrical connectivity between stacked dies.
Solution Approach 2:
The encapsulant serves as an intermediary medium that simultaneously provides mechanical support, environmental protection, and electrical interconnection functions. By incorporating conductive particles into the encapsulant, the patent creates a multi-functional material that mediates between structural and electrical requirements without requiring separate via structures.
2Reliability
If through silicon vias (TSVs) or through hole vias (THVs) are used for vertical electrical interconnections, then electrical connectivity is achieved, but manufacturing costs increase
Solution Approach 1:
The patent merges multiple manufacturing processes into a single encapsulation step. The conductive particles are mixed into the encapsulant material before molding, combining the encapsulation process with the interconnect formation process. This eliminates separate via drilling, lining, and filling operations, significantly reducing manufacturing complexity and cost.
Solution Approach 2:
The patent uses inexpensive conductive particles (such as metal powders or conductive fillers) embedded in the encapsulant as a cost-effective alternative to expensive electroplated copper vias. These simple particulate materials provide sufficient conductivity for the application while being much cheaper than traditional via fill materials and processing.
3Reliability
If through silicon vias (TSVs) or through hole vias (THVs) are used for vertical electrical interconnections, then electrical connectivity is achieved, but defects like voids and cracking occur
Solution Approach 1:
The patent changes the physical state and distribution of conductive material from concentrated via structures to dispersed particles within a matrix. This parameter change in material distribution eliminates stress concentration points that cause cracking and avoids void formation associated with via filling. The particulate dispersion provides continuous conductive pathways without the defects inherent in via-based structures.
4Productivity
If smaller die size is achieved through front-end process improvements, then device performance increases, but packaging complexity increases
Solution Approach 1:
The encapsulant is designed to perform multiple functions simultaneously: mechanical support, environmental protection, thermal management, and electrical interconnection. This multi-functionality reduces packaging complexity by eliminating the need for separate interconnect structures, allowing smaller die to be packaged more simply through the stud bump and conductive encapsulant approach.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces manufacturing time and costs, enhances reliability by minimizing stress and voids, and improves the production yield of semiconductor devices with smaller footprints and higher performance.
Implementation Method 1
forming a conductive layer outside a footprint of the semiconductor die
Implementation Method 2
depositing an encapsulant over the semiconductor die and around the first stud bump
Data Source
AI summary
A semiconductor device is made by forming a conductive layer over a temporary carrier. The conductive layer includes a wettable pad. A stud bump is formed over the wettable pad. The stud bump can be a stud bump or stacked bumps. A semiconductor die is mounted to the carrier. An encapsulant is deposited over the semiconductor die and around the stud bump. A first interconnect structure is formed over a first surface of the encapsulant. The first interconnect structure includes a first IPD and is electrically connected to the stud bump. The carrier is removed. A second interconnect structure is formed over a second surface of encapsulant opposite the first interconnect structure. The second interconnect structure includes a second IPD. The first or second IPD includes a capacitor, resistor, or inductor. The semiconductor devices are stackable and electrically connected through the stud bump.