Vertical Interconnect Routing for 3D Transistor Density
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Solution Overview
Problem
Current semiconductor manufacturing techniques face challenges in scaling transistors beyond single-digit nanometer nodes, particularly in achieving higher density and efficiency in two-dimensional circuits, as they struggle to transition to three-dimensional integration for logic chips, which is more complex than in flash memory applications.
Innovation Solution
The development of a semiconductor device with vertically stacked transistors and advanced microfabrication methods, including the use of pad structures with core and peripheral areas, and vertical interconnect structures that allow for 360-degree access and contact with gate, source, and drain regions, enabling efficient current flow and increased transistor density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If two-dimensional circuits are used to scale transistors per unit area, then transistor density increases, but routing congestion and manufacturing complexity increase significantly at single-digit nanometer nodes
Solution Approach 1:
The patent transitions from two-dimensional planar circuits to three-dimensional vertical circuits by stacking transistors vertically. Multiple transistor layers are stacked above a common substrate, with vertical interconnect structures (vias) connecting different layers. This dimensional change allows continued scaling of transistor density without proportionally increasing routing complexity, as vertical stacking provides additional spatial freedom for interconnect routing.
2Quantity of substance
If three-dimensional vertical transistor stacking is implemented, then transistor density and layout flexibility improve, but manufacturing precision requirements increase
Solution Approach 1:
The fabrication process is divided into discrete sequential steps: forming alternating semiconductor and dielectric layers, patterning gate electrodes, creating vertical interconnect access holes, and filling with conductive materials. Each step builds upon the previous layer, allowing precise control and inspection at intermediate stages. This segmented approach to layer-by-layer fabrication enables high vertical stacking density while maintaining manufacturability through standardized process modules.
3Adaptability or versatility
If vertical interconnect structures are used to access stacked transistors, then routing options increase, but the number of interconnect structures and manufacturing steps increase
Solution Approach 1:
The vertical interconnect structures (via holes filled with conductive material) serve multiple functions: they provide electrical connection between stacked transistor layers, enable routing flexibility for source, drain, and gate terminals, and can be positioned at various radial locations around the channel structure. The same via formation process is used for different interconnect purposes, reducing the need for separate specialized structures and simplifying the overall manufacturing process despite the increased routing capabilities.
Data Source
AI summary
A semiconductor device can include a pad layer including at least one pad structure having a core area surrounded by a peripheral area, and a transistor over the core area. The transistor includes a channel structure extending vertically and a gate structure all around a sidewall portion of the channel structure. The channel structure has a source region and a drain region on opposing ends of a vertical channel region. The channel structure is configured to be electrically coupled to the pad structure. The semiconductor device can further include a first vertical interconnect structure that contacts a top surface of the channel structure, a second vertical interconnect structure that contacts the peripheral area and is configured to be coupled to a bottom surface of the channel structure via the pad structure, and a third vertical interconnect structure that is positioned away from the channel structure and contacts the gate structure.