Vertical Interconnector End Geometry for Thin Semiconductor Packages
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Solution Overview
Problem
Conventional semiconductor packages face challenges in achieving a thinner form factor while maintaining high performance and preventing connection failures due to the sweeping phenomenon of vertical interconnectors, which can lead to misalignment with redistribution layers.
Innovation Solution
The semiconductor package design includes vertical interconnectors with an expanded second end portion, a molding layer exposing the interconnector surface, and a redistribution layer contacting the expanded surface, ensuring a wider contact area to prevent connection failures and maintain alignment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of stationary object
If vertical interconnectors are used in a fan-out package to reduce package thickness, then the package size is reduced, but connection failures occur due to the sweeping phenomenon causing misalignment with redistribution layers
Solution Approach 1:
The vertical interconnector is designed with non-uniform cross-sectional dimensions, featuring a first cross-sectional dimension at the first end that is smaller than a second cross-sectional dimension at the second end. This local variation in geometry compensates for the sweeping phenomenon by providing a larger contact area at the redistribution layer interface, thereby maintaining connection reliability while enabling reduced package thickness
Solution Approach 2:
The cross-sectional dimensions of the vertical interconnector are deliberately changed along its length, with the first cross-sectional dimension being smaller than the second cross-sectional dimension. This parameter change addresses the sweeping phenomenon by creating a tapered profile that ensures proper alignment and contact with the redistribution layer despite lateral displacement during the molding process
2Reliability
If the cross-sectional dimension of vertical interconnectors is increased to prevent misalignment, then connection reliability improves, but the complexity of the interconnector structure increases
Solution Approach 1:
Instead of uniformly increasing the cross-sectional dimension throughout the vertical interconnector, the invention applies a localized dimensional increase only at the second end where the interconnector contacts the redistribution layer. This targeted approach improves connection reliability while minimizing the overall structural complexity and material usage
Data Source
AI summary
A semiconductor package includes at least one semiconductor chip disposed in such a way that an active surface with chip pads faces a redistribution layer, vertical interconnectors extending in a vertical direction from the chip pads toward the redistribution layer, wherein each of the vertical connectors has a first end portion that is connected to a corresponding chip pad and a second end portion that is disposed on an opposite end of each vertical interconnector in relation to the first end portion, and a molding layer covering the semiconductor chip and the vertical interconnectors while exposing a surface of each of the second end portions of the vertical interconnectors, wherein the redistribution layer is formed over the molding layer, the redistribution layer having a redistribution land that is in contact with the surface of the second end portion, and wherein a width of the surface of the second end portion is greater than a width of an extension portion between the first end portion and the second end portion of each vertical interconnector.