Vertical Interconnectors for Thin Semiconductor Packages
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Solution Overview
Problem
Semiconductor packages face challenges in achieving a balance between high performance and small volume, with existing fan-out packages using vertical wires struggling to efficiently connect semiconductor chips while minimizing thickness and preventing process defects.
Innovation Solution
A semiconductor package design that includes a semiconductor chip with vertical interconnectors extending towards a redistribution conductive layer, a molding layer exposing the interconnectors' ends, landing pads connecting to these ends, and a redistribution insulating layer with openings to facilitate connection, allowing for a thin package structure and improved electrical alignment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of stationary object
If a fan-out package using vertical wires is employed, then the semiconductor package thickness is reduced, but alignment precision between interconnectors and landing pads deteriorates
Solution Approach 1:
The patent implements a nested structure where the molding layer is formed to expose only the lower ends of the vertical interconnectors, and the redistribution insulating layer is subsequently formed with openings that expose the upper ends. This nested layering approach allows precise alignment by controlling the exposure of interconnector ends at different stages, thereby resolving the alignment precision issue while maintaining thin package thickness.
Solution Approach 2:
The patent applies preliminary action by forming the molding layer first to expose the lower ends of vertical interconnectors, then forming landing pads in precise alignment with these exposed ends. Subsequently, the redistribution insulating layer is formed with openings that align with the upper ends of interconnectors. This sequential preliminary preparation of alignment references at each stage ensures high manufacturing precision throughout the process.
2Volume of stationary object
If vertical interconnectors are used to reduce package size, then the package volume is minimized, but process defects increase due to connection difficulties
Solution Approach 1:
The patent segments the connection process into distinct stages: first, the molding layer is formed to expose lower ends of vertical interconnectors for landing pad formation; second, the redistribution insulating layer is formed to expose upper ends for redistribution conductive layer formation. This segmentation allows each connection interface to be independently optimized and controlled, reducing process defects while maintaining compact package volume.
Solution Approach 2:
The patent introduces intermediate structures (molding layer and redistribution insulating layer) that act as mediators between the vertical interconnectors and the external environment. These intermediary layers provide controlled exposure of interconnector ends, facilitating reliable electrical connections while maintaining the compact vertical interconnector structure that minimizes package volume.
3Length of stationary object
If a thin package structure is implemented, then the package thickness is reduced, but alignment margins are reduced leading to connection errors
Solution Approach 1:
The patent resolves the alignment margin issue by transitioning from a two-dimensional planar alignment problem to a three-dimensional controlled exposure problem. By using the molding layer and redistribution insulating layer to selectively expose interconnector ends at different vertical positions, the patent creates additional vertical dimension control that compensates for reduced horizontal alignment margins in thin packages.
Data Source
AI summary
A semiconductor package may include: at least one semiconductor chip disposed such that an active surface on which a plurality of chip pads are disposed faces a redistribution conductive layer; a plurality of vertical interconnectors, each with one end connected to a respective chip pad, extending in a vertical direction toward the redistribution conductive layer; a molding layer covering the semiconductor chip and the vertical interconnectors while exposing an other end of each of the vertical interconnectors that is not connected to the chip pad; a plurality of landing pads disposed over the molding layer, and each connected to the other end of each of the vertical interconnectors; a redistribution insulating layer covering the molding layer with an opening that collectively exposes the landing pads; and the redistribution conductive layer that extends over the molding layer and the redistribution insulating layer while being connected to each of the landing pads.