Vertical Interconnects in IC Packaging via Single Integral Structure
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Solution Overview
Problem
Current integrated circuit packaging technologies face challenges in achieving miniaturization, increased density, and cost reduction while maintaining reliability and performance, particularly in portable electronic devices, as they require complex processes that lead to contamination and inefficiencies.
Innovation Solution
The development of an integrated circuit packaging system that includes a base carrier with a hole, a mounted base integrated circuit, and an encapsulation with a corresponding hole, forming a single integral interconnection structure through both holes, which eliminates contamination and simplifies the manufacturing process by using a single process to form top and bottom terminals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple separate processes are used to form top and bottom terminals, then manufacturing flexibility is maintained, but contamination occurs and manufacturing complexity increases
Solution Approach 1:
The patent combines the formation of top and bottom terminals into a single integrated process step. The interconnection structure is formed as one continuous operation that simultaneously creates both terminals, eliminating the need for separate processing steps. This merging approach prevents contamination between steps and simplifies the overall manufacturing process while maintaining reliability.
2Volume of moving object
If package size is reduced for miniaturization, then portability is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent transitions from planar interconnection structures to three-dimensional vertical interconnection structures. By forming interconnection structures that extend vertically through the package rather than only horizontally, the design achieves miniaturization in the planar dimensions while maintaining functional precision through the added vertical dimension. This allows smaller package footprints without compromising manufacturing precision.
3Quantity of substance
If integrated circuits are stacked to increase density, then space utilization is improved, but structural integrity challenges arise
Solution Approach 1:
The patent implements a nested structure where multiple integrated circuits are stacked vertically within a single package, with each circuit embedded in its own encapsulation layer. The interconnection structures penetrate through multiple encapsulation layers to establish electrical connections between stacked circuits. This nested arrangement maximizes space utilization while the continuous interconnection structures provide structural reinforcement that maintains package integrity.
Data Source
AI summary
A method of manufacture of an integrated circuit packaging system includes: providing a base carrier having a base carrier hole from a base carrier interconnection side to a base carrier device side; mounting a base integrated circuit over the base carrier; forming an encapsulation over the base carrier covering the base integrated circuit, the encapsulation having an encapsulation top side and having an encapsulation hole directly over the base carrier hole; and forming an interconnection structure as a single integral structure through the base carrier hole and the encapsulation hole, the interconnection structure directly on the encapsulation top side and directly on the base carrier interconnection side.