Vertical Interconnects for Stacked Non-Volatile Memory
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Solution Overview
Problem
Current semiconductor devices, particularly non-volatile memory devices, face challenges such as short channel effects, sub-threshold slope non-scaling, and increased power dissipation as they approach sizes less than 100 nm, and existing non-volatile memory technologies like Fe-RAM, MRAM, and PCRAM have limitations in compatibility, size, and reliability.
Innovation Solution
A method and structure for forming a vertical interconnect structure in a stacked resistive switching device, which includes defining regions on a substrate, depositing dielectric materials, and forming bottom and top wiring structures with via structures to connect memory cells to control circuitry, reducing the need for multiple pattern and etch steps and enabling a multilayer vertically stacked non-volatile memory device with high density and reduced feature size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If transistor-based memories are scaled down to less than 100 nm, then device density is improved, but short channel effects and power dissipation increase
Solution Approach 1:
The patent transitions from planar 2D memory structures to vertically stacked 3D structures. Multiple memory layers are stacked in the vertical dimension, allowing continued density improvement without further lateral scaling. This dimensional transition avoids the short channel effects that plague sub-100nm planar transistors while maintaining high device density.
2Reliability
If multiple separate via structures are used to connect each memory layer to control circuitry, then electrical connection is ensured, but fabrication complexity and process steps increase
Solution Approach 1:
The patent merges multiple separate via structures into a single shared via structure that serves all memory layers. Instead of forming individual vias for each layer, one via structure is formed that provides electrical connection to control circuitry for the entire stack, dramatically reducing fabrication steps while ensuring proper electrical connections.
Solution Approach 2:
The single via structure performs multiple functions simultaneously - it provides electrical connection for all memory layers to control circuitry, serves as a common interconnect, and reduces the overall via count. This multi-functional approach simplifies the device structure and fabrication process.
3Adaptability or versatility
If conventional non-volatile memory technologies (Fe-RAM, MRAM, PCRAM) are used, then memory functionality is achieved, but compatibility with CMOS fabrication or device size increases
Solution Approach 1:
The patent employs a composite structure combining resistive switching materials with standard CMOS-compatible dielectric and conductive materials. The resistive switching layer is integrated with silicon-based CMOS processes, creating a hybrid structure that achieves non-volatile memory functionality while maintaining compatibility with existing CMOS fabrication infrastructure.
Data Source
AI summary
A method of forming a vertical interconnect for a memory device. The method includes providing a substrate having a surface region and defining a cell region, a first peripheral region, and a second peripheral region. A first thickness of dielectric material is formed overlying the surface region. A first bottom wiring structure spatially configured to extend in a first direction is formed overlying the first dielectric material for a first array of devices. A second thickness of a dielectric material is formed overlying the first wiring structure. The method includes forming an opening region in the first peripheral region. The opening region is configured to extend in a portion of at least the first thickness of dielectric material and the second thickness of dielectric material to expose a portion of the first wiring structure and to expose a portion of the substrate. A second bottom wiring material is formed overlying the second thickness of dielectric material and filling the opening region to form a vertical interconnect structure in the first peripheral region. A second bottom wiring structure is formed from the second wiring material for a second array of devices. The second bottom wiring structure is separated from the first bottom wiring structure by at least the second thickness of dielectric material and spatially configured to extend in the first direction. The first wiring structure and the second wiring structure are electrically connected by the vertical interconnect structure in the first peripheral region to a control circuitry on the substrate.