Vertical Inverter Layout for High-Density 4F² Logic Cells
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Solution Overview
Problem
Microelectronic device designers face challenges in increasing integration density and reducing surface area while maintaining performance, as the number of transistors in control logic devices increases, requiring more compact and efficient designs for memory devices.
Innovation Solution
The implementation of an array of vertical inverters with a first and second vertical transistor, where the second transistor is horizontally neighboring the first and isolated by a dielectric material, forming a 4F^2 cell size, allowing for a smaller horizontal footprint and increased density by forming the transistors vertically over the base material rather than within it.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the number of transistors in control logic devices is increased to improve functionality, then the device complexity and transistor count increase, but the surface area per transistor must be decreased leading to reduced integration density and increased overall device area
Solution Approach 1:
The patent transitions from planar (2D) transistor layouts to vertically stacked (3D) transistor structures. Multiple transistors are stacked vertically within a single footprint, allowing increased transistor count without proportionally increasing device area. This dimensional change enables higher integration density while maintaining control logic functionality.
Solution Approach 2:
The patent implements nested structures where transistors are stacked within vertical columns, with gate structures wrapping around channel regions. Multiple functional elements are nested within each other vertically, maximizing the use of three-dimensional space within the device footprint.
2Quantity of substance
If the dimensions of individual features are reduced to increase integration density, then the feature size decreases, but manufacturing precision requirements increase
Solution Approach 1:
By moving to vertical stacking, the patent reduces the horizontal footprint requirements while maintaining functional transistor dimensions. The vertical dimension provides additional space without compromising the manufacturing precision of individual feature dimensions in the lateral plane.
Solution Approach 2:
The patent divides the device into multiple vertical layers or decks, with each layer containing segmented transistor structures. This segmentation allows independent optimization and manufacturing of each layer, reducing the cumulative precision requirements compared to monolithic planar structures.
3Device complexity
If transistors are arranged in planar configurations to simplify design, then the design complexity is reduced, but the surface area occupied by each transistor increases
Solution Approach 1:
The patent employs vertical stacking to achieve compact transistor footprints while maintaining relatively straightforward fabrication processes using adapted CMOS technology. The vertical arrangement naturally simplifies routing and interconnect design compared to dense planar layouts.
Data Source
AI summary
A microelectronic device comprises vertical inverter comprising a pillar structure vertically extending above a first conductive line. The pillar structure comprises a first vertical transistor vertically overlying and in electrical communication with the first conductive line, a second conductive line vertically overlying the first conductive line and electrically isolated from the first conductive line by a dielectric material, the second conductive line configured to be coupled to a ground structure, a second vertical transistor horizontally neighboring the first vertical transistor and in electrical communication with the second conductive line, the second vertical transistor horizontally spaced from the first vertical transistor by the dielectric material, and at least one electrode horizontally extending along a channel region of the first vertical transistor and an additional channel region of the second vertical transistor. Related microelectronic devices and electronic systems are also described.