Vertical Inverter Layout for Higher Thin-Film Transistor Density
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Solution Overview
Problem
Conventional display panels have an insufficient integration degree of thin film transistors, limiting their performance and requiring a solution to increase the number of transistors within a limited space.
Innovation Solution
A vertical inverter and semiconductor device design that includes a first thin film transistor with an N-type active layer and a second thin film transistor with a P-type active layer, both disposed on an insulation substrate, allowing for a layered arrangement that increases the integration density of thin film transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If more thin film transistors are arranged within a limited space to increase integration degree, then the integration degree is improved, but the device complexity increases
Solution Approach 1:
The patent transitions from a planar arrangement of thin film transistors to a vertical three-dimensional structure. The active layer is folded back upon itself to form a vertical configuration, allowing multiple transistor channels to be stacked within the same footprint area. This dimensional change enables higher integration density without proportionally increasing device complexity, as the vertical stacking reuses the same lateral space more efficiently.
Solution Approach 2:
The patent implements a nested structure where the active layer is folded back to create inner and outer channels that are spatially nested within the same device footprint. The inner channel is formed by folding the active layer back, creating a configuration where one channel is effectively nested within the spatial envelope of another, maximizing the use of available space while maintaining manageable device complexity through systematic structural repetition.
2Quantity of substance
If the active layer is folded back to form a vertical structure, then the integration degree is improved, but the manufacturing precision requirements increase
Solution Approach 1:
The patent divides the active layer into distinct segments - an inner channel portion and an outer channel portion - that are formed through separate processing steps. This segmentation allows each channel to be independently defined and controlled, reducing the cumulative precision errors that would arise from attempting to form a complex folded structure in a single step. The segmented approach enables modular manufacturing with relaxed precision requirements compared to monolithic vertical structures.
Solution Approach 2:
The patent performs preliminary patterning and doping actions to define the inner and outer channels before final device assembly. By pre-establishing the spatial configuration and electrical properties of each channel segment through sequential processing steps, the manufacturing process accommodates the vertical structure without requiring ultra-high precision in a single critical step, thereby reducing overall manufacturing precision requirements.
Data Source
AI summary
The present disclosure provides a vertical inverter and a semiconductor device including the vertical inverter, and the vertical inverter includes an insulation substrate, a first thin film transistor, and a second thin film transistor. By a layered arrangement of the first and second thin film transistors of the vertical inverter, more thin film transistors can be arranged within the limited space, so that the integration degree of the thin film transistors in the semiconductor device can be improved.