Vertical I/O Routing in Bonded Wafers Without Deep Oxide Etching
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Solution Overview
Problem
Conventional methods for fabricating connections between layers in integrated circuits, such as CCDs, are time-consuming and costly due to the need for aggressive etching of thick oxide layers, which can lead to mechanical stress and processing complications.
Innovation Solution
Direct bonding hybridization (DBH) is used in conjunction with foundry metal layers to vertically route I/O signal paths, allowing for closer placement of I/O pads to the top layer and reducing processing time and risk by avoiding deep etches, enabling efficient integration of I/O pads in a visible imaging array.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If aggressive etching is used to remove thick oxide layers over aluminum I/O pads, then the oxide layer is removed, but processing time increases and mechanical stress increases
Solution Approach 1:
The patent applies preliminary action by forming through-silicon vias (TSVs) and establishing vertical interconnections before bonding the wafers together. This allows the I/O pads to be accessed through the bonded interface rather than requiring post-bonding etching through thick oxide layers, thereby eliminating the time-consuming aggressive etching step while maintaining manufacturing precision
2Manufacturing precision
If aggressive etching is used to remove thick oxide layers over aluminum I/O pads, then the oxide layer is removed, but mechanical stress and processing complications increase
Solution Approach 1:
The patent performs the vertical routing and I/O pad access preparation before wafer bonding, eliminating the need for post-bonding aggressive etching. This preliminary action prevents mechanical stress and processing complications that would arise from etching through thick oxide layers after the wafers are bonded, thereby improving reliability while maintaining the ability to remove oxide layers when needed
3Ease of manufacture
If conventional layer-to-layer connections are fabricated, then interconnections are established, but the process is time-consuming and costly
Solution Approach 1:
The patent transitions from conventional planar layer-to-layer connections to vertical three-dimensional interconnections using through-silicon vias (TSVs). This dimensional change allows signals to be routed vertically through the substrate thickness, enabling more direct and shorter connection paths that reduce fabrication time and cost while maintaining ease of manufacture through standardized TSV processing
4Ease of manufacture
If I/O pads are placed farther from the top layer, then routing is simpler, but cycle time increases and integration efficiency decreases
Solution Approach 1:
The patent uses vertical through-silicon vias to route I/O signals directly to pads located on the backside or near-surface of the bonded wafer assembly. This three-dimensional routing approach allows I/O pads to be positioned optimally for device performance while maintaining simple and efficient routing paths, thereby improving integration efficiency and productivity without sacrificing routing simplicity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces cycle time and process risk by allowing vertical routing of I/O signal connections through foundry layers, facilitating quicker and more reliable integration of I/O pads without the need for deep etching, thus improving the efficiency of integrated circuit assembly.
Implementation Method 1
directly bonding the first and second wafers at the direct bonding posts to form an assembly, wherein a direct bonding interface is formed at bonding surfaces of the first and second wafers
Data Source
AI summary
Methods and apparatus for an assembly having directly bonded first and second wafers where the assembly includes a backside surface and a front side surface. The first wafer includes IO signal connections vertically routed to the direct bonding interface by a first one of the bonding posts on the first wafer bonded to a first one of the bonding posts on the second wafer. The second wafer includes vertical routing of the IO signal connections from first one though the bonding posts on the second wafer to IO pads on a backside surface of the assembly.