Vertical JFET Die Layout With Integrated Anti-Parallel Diode Cells
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Solution Overview
Problem
Current vertical junction field-effect transistors (JFETs) built on silicon carbide (SiC) face challenges in integrating source-drain anti-parallel diode cells effectively at the die level, which limits their performance in high-power conversion applications.
Innovation Solution
The integration of trench gate vertical JFETs with source-drain anti-parallel diode cells at the die level, featuring a substrate with trenches and mesas, where a floating closed loop mesa electrically isolates the anode region from the gate regions, allowing for the formation of anti-parallel diode cells within the JFETs without altering the stripe cell structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If source-drain anti-parallel diode cells are integrated into vertical JFETs at die level, then reverse current conduction performance is improved, but device structure complexity increases
Solution Approach 1:
The patent merges the diode cell structure with the vertical JFET structure by integrating the anode region into the drain-cathode region and sharing common regions (source regions, drift regions, buffer regions) between the JFET and diode cell. This merging approach allows the anti-parallel diode to be formed within the same device footprint without requiring separate discrete components, thereby improving reverse current conduction while managing structural complexity through region sharing.
Solution Approach 2:
The patent creates a multi-functional device structure where the same physical regions serve dual purposes: the drain-cathode region functions as both the JFET drain and the diode anode, while source regions serve as both JFET sources and diode cathodes. This universal design allows a single integrated structure to provide both JFET switching functionality and diode reverse conduction functionality, resolving the contradiction between performance improvement and structural complexity.
2Reliability
If anti-parallel diode cells are integrated within vertical JFETs, then saturation current density is reduced, but manufacturing complexity increases
Solution Approach 1:
The patent employs preliminary action by forming all the necessary regions (anode, cathode, source, drift, buffer) in a single integrated fabrication sequence before final device assembly. The doping profiles and region geometries are established during the initial processing steps, allowing the anti-parallel diode structure to be created alongside the JFET structure without requiring additional complex manufacturing steps or post-fabrication assembly operations.
3Reliability
If floating closed loop mesa is used to electrically isolate anode region from gate regions, then device performance is enhanced, but fabrication complexity increases
Solution Approach 1:
The patent introduces a floating closed loop mesa structure as an intermediary element that provides electrical isolation between the anode region and the gate regions. This mesa structure acts as a physical and electrical barrier that prevents unwanted charge carrier injection from the gate into the anode region, thereby enhancing device performance by improving isolation characteristics without requiring complex external isolation structures or additional processing steps.
Data Source
AI summary
This disclosure relates to a semiconductor die and a method for fabrication of a semiconductor die. The disclosed semiconductor die comprises a substrate having a drain-cathode region, a plurality of trenches and mesas, a first anode trench, and a first floating closed loop mesa surrounding the first anode trench. The semiconductor die further comprises a first anode region under the first anode trench, a plurality of source regions extending from top surfaces into the plurality of mesas, and a plurality of gate regions extending along a bottom surface and portions of sidewalls of each of the plurality of trenches. The first floating closed loop mesa electrically isolates the first anode region from the plurality of gate regions, and the first anode region electrically couples to the plurality of source regions to integrate an anti-parallel diode cell within vertical junction field-effect transistors (JFETs).