Capacitively Coupled Vertical JFET Gate Structure for High-Voltage Reliability
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Solution Overview
Problem
Conventional silicon carbide-based junction field effect transistors (JFETs) face limitations due to gate electrodes that cannot withstand high voltages and have low reliability, restricting their application as power switches, and suffer from low mobility and poor performance due to conducting channels near the material surface and poor quality gate dielectric layers.
Innovation Solution
A vertical coupling capacitance gate-controlled junction field effect transistor with a floating top gate indirectly controlled by a coupling capacitance upper electrode through a dielectric layer, featuring internal conducting paths to avoid surface mobility issues and high electric fields, using a novel structure that includes a base, bottom gates, a top gate, a dielectric layer, and a coupling capacitance upper electrode.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional gate electrode structure is used in SiC JFET, then the device structure is simple, but the gate cannot withstand high voltages and has low reliability
Solution Approach 1:
The gate structure is divided into multiple segments: bottom gate electrodes, top gate electrode, and coupling capacitance gate electrode. This segmentation allows each component to perform its specific function - the bottom gates provide basic gate control, the top gate enhances voltage withstanding capability, and the coupling capacitance gate enables high voltage operation with improved reliability.
Solution Approach 2:
The patent implements a nested gate structure where the top gate electrode is positioned above the bottom gates, and the coupling capacitance gate electrode is positioned above the top gate. This nested arrangement creates multiple layers of gate control, with each layer contributing to the overall voltage withstanding capability and reliability of the device.
2Reliability
If conducting channel is located near the material surface, then the device structure is simpler, but mobility is low and performance is poor
Solution Approach 1:
The patent transitions from a surface-level conducting channel to a vertically positioned conducting channel within the semiconductor substrate. By moving the channel formation to a different spatial dimension (from surface to internal volume), the device achieves higher carrier mobility and better performance while maintaining manufacturing feasibility through controlled doping processes.
3Reliability
If gate dielectric layer quality is poor, then the manufacturing process is simpler, but the device reliability and voltage withstanding capability are reduced
Solution Approach 1:
The patent employs a composite gate dielectric structure consisting of multiple layers with different material properties. This composite approach combines the advantages of different dielectric materials to achieve both high voltage withstanding capability and good manufacturing characteristics, balancing reliability requirements with fabrication ease.
4Adaptability or versatility
If conventional JFET structure is used, then the device is normally-on, but negative voltage must be applied to turn off, limiting power switch application
Solution Approach 1:
The patent implements a dynamically controllable gate structure where the coupling capacitance gate electrode can apply positive voltages to turn off the device. This dynamic control mechanism transforms the device from a normally-on configuration requiring negative voltage turn-off to a normally-on device that can be turned off with positive voltage, greatly enhancing its adaptability for power switch applications.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The transistor can withstand higher voltages without conducting, maintains high reliability, and achieves improved performance by avoiding surface mobility issues and enhancing dielectric layer quality, resulting in larger saturation current and lower conducting resistance.
Implementation Method 1
a top gate of a second doping type, formed inside the base, where the top gate is located above an interval between the two bottom gates, and an interval is formed between the top gate and the bottom gates; a dielectric layer, formed on the base and located on the top gate; and a coupling capacitance upper electrode, formed on the dielectric layer; where the top gate is indirectly controlled by the coupling capacitance upper electrode spaced with the dielectric layer
Data Source
AI summary
Disclosed are a vertical coupling capacitance gate-controlled junction field effect transistor and a manufacturing method thereof. The vertical coupling capacitance gate-controlled junction field effect transistor includes a base of a first doping type; two bottom gates of the second doping type, formed inside the base and spaced apart in the lateral direction; a top gate of the second doping type, formed inside the base, where the top gate is located above the interval between the two bottom gates, and an interval is formed between the top gate and the bottom gate; a dielectric layer, formed on the base and located on the top gate; and a coupling capacitance upper electrode, formed on the dielectric layer; where the top gate is indirectly controlled by the coupling capacitance upper electrode spaced with the dielectric layer.