Vertical JFET Gate Region Shaping for Channel Length Control
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The existing methods for manufacturing vertical JFETs face challenges in achieving stable production yields due to difficulties in controlling the angle of sloped sidewalls, which affects the channel width and off-state performance.
Innovation Solution
A semiconductor device with a vertical JFET is manufactured by forming a gate region with a quadrangular cross-section through impurity ion implantation, followed by specific etching processes to create a parallel lower surface and a sloping upper surface, thereby enhancing the channel length and off-state performance without reducing production yield.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a trench with sloped sidewall is formed by ion implantation to increase channel length, then off-state performance is improved, but production yield becomes unstable due to difficulty in controlling sidewall angle
Solution Approach 1:
The gate region is divided into two distinct surfaces: a lower surface formed parallel to the substrate surface, and an upper surface with a slope from side surface to center. This segmentation allows each surface to be controlled independently through different etching processes, resolving the contradiction between achieving long channel length (for off-state performance) and controlling dimensional precision.
Solution Approach 2:
Different regions of the gate region are given different geometric properties: the lower surface has a flat, parallel orientation for precise channel length definition, while the upper surface has a sloped geometry. This local differentiation enables the gate to simultaneously achieve the channel length extension needed for off-state performance and the geometric control needed for manufacturing precision.
2Reliability
If channel length is increased to improve off-state performance, then device performance is enhanced, but production yield decreases due to variations in channel width
Solution Approach 1:
By segmenting the gate region into a lower surface and an upper surface with distinct geometric characteristics, the invention enables precise control of channel length through the lower surface while the upper surface provides the necessary slope for proper device operation. This segmentation ensures that increased channel length does not come at the cost of production yield.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in a vertical JFET with improved off-state performance and reduced variations in channel length, maintaining stable production yields by controlling the etching process to ensure precise separation between the source and gate regions.
Implementation Method 1
a gate region having a quadrangular shape at the cross-section taken along a channel width direction is formed below a source region by impurity ion implantation
Implementation Method 2
second etching having an etching rate lower at the side surface of the gate region than at the center of the gate region is then performed to process the upper surface of the gate region
Data Source
AI summary
To provide a semiconductor device having a vertical JFET excellent in off-state performance without reducing a production yield. A gate region quadrangular in the cross-section along a channel width direction is formed below a source region by impurity ion implantation. By first etching, the source region over the upper surface of the gate region is removed to separate therebetween. Then, the upper surface of the gate region is processed by second etching having an etching rate lower at the side surface than at the center of the gate region. The resulting gate region has a lower surface parallel to the substrate surface and an upper surface below a boundary between the source region and the channel formation region and having, in the cross-section along the channel width direction, a downward slope from the side surface to the center. As a result, a channel length with reduced variations can be obtained.