Vertical JFET Ladder Termination Masking Process

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Solution Overview

Problem

Existing vertical junction field-effect transistors (JFETs) made from materials like silicon carbide (SiC) face challenges in achieving improved performance and efficient edge terminations, particularly in power electronic circuits, due to complex masking processes and limited scalability.

Innovation Solution

A simplified process using a reduced masked set to fabricate vertical JFETs with ladder terminations, where a first mask forms mesas and trenches simultaneously, a mask-less self-aligned process creates silicide source and gate contacts, and additional masks are used for metallization and passivation, allowing for optional angled doping and varying trench and mesa widths between active and termination regions.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If traditional multi-mask processes are used to fabricate vertical JFETs with edge terminations, then manufacturing precision and device performance can be improved, but device complexity and manufacturing cost increase significantly

Engineering Contradiction:
Improveedge termination precisionVSAvoidmasking process complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent combines multiple masking operations into a single mask that simultaneously defines both the active cell region and the termination region features. This single mask approach merges what would traditionally require multiple separate masking steps, reducing process complexity while maintaining the precision needed for edge terminations.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The single mask used in the invention serves multiple functions: it defines the active cell region, defines the termination region, and establishes the geometric relationships between different device regions. This multi-functional mask replaces what would traditionally require several specialized masks, simplifying the overall fabrication process.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Reliability

If complex masking processes are used to achieve precise edge terminations, then device performance improves, but productivity and manufacturing efficiency decrease

Engineering Contradiction:
Improvedevice performanceVSAvoidmanufacturing efficiency
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

By merging multiple masking steps into a single masking operation, the patent reduces the total number of process steps required to fabricate vertical JFETs with edge terminations. This consolidation maintains the precision needed for reliable device performance while significantly improving manufacturing throughput and efficiency.

Inventive Principle:
Principle #5Merging (Combining)

3Manufacturing precision

If traditional fabrication processes are used, then manufacturing precision can be maintained, but ease of manufacture and scalability are limited

Engineering Contradiction:
Improvetrench and mesa dimensionsVSAvoidfabrication simplicity
Core Design Contradiction:
Manufacturing precisionVSEase of manufacture

Solution Approach 1:

The patent merges the definition of trenches and mesas in both active and termination regions into a single masking and etching operation. This approach maintains precise dimensional control for all features while simplifying the fabrication process, making it easier to manufacture and more scalable to production volumes.

Inventive Principle:
Principle #5Merging (Combining)

4Manufacturing precision

If multiple masks are used to form different regions, then manufacturing precision improves, but loss of time and process duration increase

Engineering Contradiction:
Improveregion definition accuracyVSAvoidfabrication time
Core Design Contradiction:
Manufacturing precisionVSLoss of time

Solution Approach 1:

The patent combines multiple sequential masking operations into a single simultaneous masking operation. This eliminates the time required for multiple mask applications, alignments, and etching steps, while still achieving the precise region definitions needed for high-performance vertical JFETs with edge terminations.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS10367099B2Trench vertical JFET with ladder termination
Publication Date: 2019.07.30 UNITED SILICON CARBIDE
  • US10367099B2 patent drawing
  • US10367099B2 patent drawing
  • US10367099B2 patent drawing

AI summary

A vertical JFET with a ladder termination may be made by a method using a limited number of masks. A first mask is used to form mesas and trenches in active cell and termination regions simultaneously. A mask-less self-aligned process is used to form silicide source and gate contacts. A second mask is used to open windows to the contacts. A third mask is used to pattern overlay metallization. An optional fourth mask is used to pattern passivation. Optionally the channel may be doped via angled implantation, and the width of the trenches and mesas in the active cell region may be varied from those in the termination region.