Vertical JFET Gate Resistance Layout for UIS Current Balancing
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Solution Overview
Problem
Conventional power semiconductor devices, particularly JFETs, face issues with unclamped inductive switching (UIS) that lead to thermal runaway and failure due to positive feedback between rising UIS current and falling voltage across the gate-drain junction, which is not effectively managed by current designs.
Innovation Solution
Incorporation of silicide block regions with high sheet resistance in the gate structure to create negative feedback, steering UIS current away from high-resistance areas and distributing it evenly across multiple gate contacts, thereby preventing thermal runaway.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional gate structure design is used, then device simplicity is maintained, but UIS current distribution is uneven causing localized heating and thermal runaway
Solution Approach 1:
The patent introduces silicide block regions with high sheet resistance at specific locations between the gate bus and gate trenches. These localized high-resistance regions create voltage drops that steer UIS current away from high-current-density areas, distributing current more evenly across multiple gate trenches. This local modification of electrical properties prevents thermal runaway while maintaining overall device simplicity.
2Speed
If gate resistance is reduced for better performance, then switching speed improves, but UIS current concentration increases causing thermal runaway
Solution Approach 1:
The silicide block regions provide automatic feedback control for UIS current distribution. When UIS current flows, voltage drops across the high-resistance silicide block regions create negative feedback that steers current away from overloaded gate trenches toward underutilized ones. This self-regulating mechanism distributes UIS current evenly without affecting normal switching operation, preventing thermal runaway while maintaining fast switching speed.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enhances the ability of JFETs to handle UIS conditions by reducing localized heating and increasing the threshold for failure, ensuring more uniform current distribution and improved reliability.
Implementation Method 1
Incorporation of silicide block regions with high sheet resistance in the gate structure to create negative feedback, steering UIS current away from high-resistance areas and distributing it evenly across multiple gate contacts
Implementation Method 2
The conductive path includes a first resistivity region and at least one second resistivity region that has a higher resistivity than the first resistivity region
Data Source
AI summary
A semiconductor device includes a semiconductor layer structure that includes an active region including a plurality of gate trenches, a plurality of gate contacts in respective ones of the gate trenches, a gate pad on the semiconductor layer structure, a gate bus extending from the gate pad, and a conductive path between the gate bus and a first one of the plurality of gate contacts. The conductive path includes a first resistivity region and at least one second resistivity region that has a higher resistivity than the first resistivity region.