Vertical Junction FinFET Device for CMOS Compatibility
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Solution Overview
Problem
Conventional JFET devices face challenges in controlling short channel effects and are incompatible with mainstream CMOS fabrication techniques, limiting their manufacturing compatibility and operational efficiency.
Innovation Solution
The development of a vertical junction FinFET device is achieved by creating semiconductor fins with epitaxial regions of different conductivity types, allowing for improved control over channel lengths and compatibility with CMOS processes through precise doping and epitaxial growth methods.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If conventional JFET devices are used, then the device is simple to form and operate, but short channel effects are difficult to control
Solution Approach 1:
The patent transitions from planar JFET structure to vertical FinFET structure, adding the vertical dimension with fins extending upward from the substrate. This dimensional change enables better electrostatic control of the channel while maintaining operational simplicity through the vertical junction architecture.
Solution Approach 2:
The channel region is segmented into multiple fins rather than a single planar channel. This segmentation allows each fin to be independently controlled by the gate, improving overall control of short channel effects while maintaining the simplicity of the JFET operation principle.
2Device complexity
If conventional JFET devices are used, then the device structure is simple, but manufacture is incompatible with mainstream CMOS fabrication techniques
Solution Approach 1:
The vertical junction FinFET structure serves multiple functions: it maintains the simple JFET operational principle while simultaneously enabling compatibility with standard CMOS fabrication processes. The structure can be integrated into existing CMOS production lines using conventional epitaxial growth and doping techniques.
Solution Approach 2:
The patent modifies the structural parameters of the JFET by introducing vertical fins with specific dimensions and doping concentrations. These parameter changes enable the device to be manufactured using standard CMOS processes while retaining the essential JFET characteristics.
3Reliability
If vertical junction FinFET structure is implemented, then control over short channel effects is improved, but device structure becomes more complex
Solution Approach 1:
By introducing the vertical dimension with fins extending from the substrate, the patent achieves superior electrostatic control of the channel. The vertical junction architecture provides better gate control over the channel region compared to planar structures, effectively mitigating short channel effects despite the increased structural complexity.
4Ease of manufacture
If vertical junction FinFET structure is implemented, then compatibility with CMOS techniques is improved, but manufacturing process becomes more complex
Solution Approach 1:
The vertical junction FinFET structure is designed to be compatible with existing CMOS fabrication techniques, allowing the same manufacturing infrastructure to produce both CMOS and JFET devices. The process uses standard epitaxial growth and doping methods already employed in CMOS production, minimizing the need for new manufacturing equipment or processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables effective control over short channel effects and facilitates the integration of JFET devices with CMOS techniques, enhancing manufacturing compatibility and operational efficiency.
Implementation Method 1
epitaxially growing first semiconductor material to form a first epitaxial region in contact with the second end of the fin of semiconductor material
Implementation Method 2
implanting dopant of a first conductivity-type in a semiconductor substrate to form a first doped region
Data Source
AI summary
A vertical junction field effect transistor (JFET) is supported by a semiconductor substrate that includes a source region within the semiconductor substrate doped with a first conductivity-type dopant. A fin of semiconductor material doped with the first conductivity-type dopant has a first end in contact with the source region and further includes a second end and sidewalls between the first and second ends. A drain region is formed of first epitaxial material grown from the second end of the fin and doped with the first conductivity-type dopant. A gate structure is formed of second epitaxial material grown from the sidewalls of the fin and doped with a second conductivity-type dopant.