Vertical Junctionless Transistors with Back Gate
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Solution Overview
Problem
As semiconductor memory devices become increasingly integrated, the reduced feature size leads to short channel effects and increased junction leakage current, making it difficult to control threshold voltage and manage leakage current, resulting in issues such as short battery life and higher power consumption in devices like notebook computers and degradation of data retention in nonvolatile memory devices.
Innovation Solution
The integration of III-V transistor channels with silicon, utilizing a three-dimensional vertical junctionless transistor structure and a back gate for threshold voltage tuning, along with a method that includes forming a fin device structure, a sacrificial layer, and a gate dielectric layer to overcome lattice mismatch issues and suppress short channel effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If feature size is reduced to increase device integration, then device integration is improved, but short channel effect and junction leakage current increase
Solution Approach 1:
The patent transitions from planar transistor structures to vertical three-dimensional structures. The channel is formed vertically along the sidewalls of sacrificial fins, creating a vertical junctionless transistor architecture. This dimensional change allows continued scaling while maintaining better control over short channel effects and reducing junction leakage current through the vertical channel design.
Solution Approach 2:
The patent introduces a sacrificial layer (e.g., silicon germanium) that serves as an intermediary structure during fabrication. This sacrificial layer is used to define the vertical channel regions and is subsequently removed to create the final transistor structure. The intermediary approach enables precise control of channel formation while managing the complexities of integrating hybrid materials with different lattice constants.
2Productivity
If feature size is reduced to increase device integration, then device integration is improved, but threshold voltage control becomes difficult
Solution Approach 1:
The vertical three-dimensional structure provides additional control dimensions for threshold voltage tuning. The back gate, positioned at the base of the vertical structure, enables effective threshold voltage control through the vertical field effect, overcoming the limitations of scaled planar devices where threshold voltage control becomes increasingly difficult.
Solution Approach 2:
The patent employs hybrid semiconductor materials with different lattice constants (e.g., III-V materials on silicon) to create vertical junctionless transistors. The composite material structure, combined with carefully engineered layer thicknesses and compositions, enables precise threshold voltage control through material property optimization while maintaining lattice mismatch management.
3Productivity
If feature size is reduced to increase device integration, then device integration is improved, but junction leakage current increases
Solution Approach 1:
The patent removes traditional source-drain junctions from the device structure by implementing a junctionless channel design. Current is modulated through the vertical channel without requiring doped junctions, thereby eliminating junction leakage current entirely. The sacrificial layer removal creates clean vertical channels free from junction-related leakage paths.
Solution Approach 2:
By transitioning to vertical channels, the patent reduces the horizontal junction area that would otherwise generate leakage current in scaled planar devices. The vertical architecture minimizes the overlap between source and drain regions, effectively reducing junction leakage while maintaining high device integration.
4Reliability
If hybrid materials are integrated to improve carrier velocity and drive current, then performance is improved, but atomic lattice mismatch problems arise
Solution Approach 1:
The patent optimizes the composition and thickness parameters of hybrid semiconductor layers to achieve lattice matching between different materials. By carefully controlling the stoichiometry of III-V materials and the thickness of buffer layers, the patent minimizes lattice mismatch effects while maintaining the high carrier velocity and drive current benefits of hybrid materials.
Solution Approach 2:
The patent employs composite material structures with graded compositions to bridge the lattice mismatch between silicon substrates and III-V channel materials. The composite approach uses intermediate buffer layers and controlled material compositions to gradually transition between lattice constants, enabling successful integration of high-performance hybrid materials while managing manufacturing challenges.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables continued scaling beyond silicon capabilities, providing higher carrier velocity and drive current while effectively managing leakage current and threshold voltage, thus improving the performance and efficiency of semiconductor devices.
Implementation Method 1
performing an oxidation process to form a thermal oxide layer in the cavity surrounding the side surface of the fin structure
Data Source
AI summary
A semiconductor device includes a silicon substrate, a silicon germanium (SiGe) layer including a lower portion extending over the silicon substrate and a fin structure protruding above the lower portion, a first dielectric layer disposed over a side surface of the fin structure and a top surface of the lower portion of the silicon germanium (SiGe) layer, an indium gallium arsenide (InGaAs) layer disposed over a surface of the first dielectric layer, a high k oxide layer disposed over a surface of the InGaAs layer, and a metal layer disposed over a surface of the high k oxide layer. The InGaAs layer includes a source region, a channel region, and a drain region. The metal layer is configured to be a first gate electrode, and the fin structure in the SiGe layer is configured to be a second gate electrode.