Vertical Laminated Magnetic Core for High-Inductance CMOS Inductors

The patent transitions from conventional planar (2D) inductor structures to a vertically-laminated (3D) core structure. The magnetic core comprises multiple ferromagnetic layers stacked vertically with alternating magnetization directions, creating a three-dimensional magnetic path that significantly increases inductance per unit area. This dimensional change allows the inductor to achieve high current carrying capacity while maintaining a compact footprint suitable for integrated power conversion devices.

The patent divides the magnetic core into multiple thin ferromagnetic layers separated by non-magnetic spacer layers. Each layer is independently magnetized in alternating directions (upward and downward), creating a segmented magnetic structure. This segmentation reduces hysteresis losses by minimizing eddy currents within each thin layer while maintaining high overall inductance through the cumulative effect of all layers working together in the magnetic circuit.

The patent achieves high current carrying capacity without increasing footprint by utilizing vertical stacking of multiple ferromagnetic layers. The alternating magnetization pattern in the vertical dimension creates efficient magnetic flux paths that maximize inductance within a small planar area. This allows the inductor to handle large currents while maintaining a compact footprint suitable for integration with CMOS transistors in three-dimensional or 2.5D chip stacking configurations.

The patent employs thin segmented ferromagnetic layers separated by non-magnetic spacers, which effectively reduces eddy current losses at high frequencies. The segmentation creates multiple small magnetic paths instead of large continuous loops, minimizing circulating currents that cause frequency-dependent losses. This structure maintains stable inductance values and low power losses even at high operating frequencies, enabling efficient high-speed power conversion in integrated devices.