Vertical LED Chip Layout for Central Light Emission and Heat Dissipation
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Solution Overview
Problem
Small-size vertical-type light emitting diode chips have relatively low luminous efficiency and poor heat dissipation, leading to reliability issues, especially when used in vehicle displays, due to shading of the light emitting surface by electrodes and complex manufacturing processes.
Innovation Solution
A small-size vertical-type light emitting diode chip design with a P-type electrode on one side, an interface structure with a high-concentration P-type semiconductor layer, an insulating layer, a bridging connected metal layer, and an N-type Ohmic contact electrode, allowing light to emit from the central region without shading, improving luminous efficiency and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the N-type electrode pad is arranged in the central region on the N-type semiconductor, then the electrode can be properly positioned, but the luminous area is shaded and luminous efficiency decreases
Solution Approach 1:
The N-type electrode pad is extracted from the central light emitting region and relocated to the peripheral region of the chip. This separation removes the shading obstacle from the luminous area while maintaining proper electrode positioning for reliable wire bonding connections.
Solution Approach 2:
The electrode pad arrangement transitions from a centralized two-dimensional layout to a peripheral distribution. By moving the electrode pad to the edge region, the patent creates spatial separation between the luminous function and electrical connection function, allowing both to perform optimally without interference.
2Productivity
If the chip size is reduced to small-size, then the display pitch can be reduced, but the heat dissipation performance deteriorates
Solution Approach 1:
The patent designs the vertical-type structure with the active layer positioned close to the substrate surface from the beginning, enabling efficient heat conduction path to be established beforehand. This preliminary structural arrangement ensures that even in small-size chips, heat can be rapidly conducted to the substrate for dissipation.
Solution Approach 2:
The patent optimizes the local thermal conduction properties by positioning the active layer adjacent to the substrate and designing the electrode structure to serve dual functions of electrical connection and heat dissipation. This localized quality enhancement ensures effective heat management in the critical region despite the overall small chip size.
3Productivity
If the chip size is reduced to small-size, then the display pitch can be reduced, but the luminous efficiency decreases
Solution Approach 1:
The patent transitions from horizontal light emission to vertical light emission by positioning the active layer vertically above the substrate. This dimensional change allows the light to emit upward through the transparent substrate without being blocked by peripheral structures, maintaining high luminous efficiency in small-size chips.
Solution Approach 2:
The N-type electrode pad is extracted from the light emitting region and placed in the peripheral area. This removal of the shading element from the luminous path enables the small-size chip to achieve high luminous efficiency by eliminating the trade-off between electrode placement and light emission area.
4Reliability
If reference lines are arranged in interdigitated finger shape above the N-type semiconductor, then current dispersion is improved, but the shading area increases
Solution Approach 1:
The reference lines are extracted from the central light emitting region and relocated to the peripheral region where the N-type electrode pad is positioned. This extraction removes the shading obstacles from the luminous area while maintaining the interdigitated finger structure for effective current dispersion in the peripheral connection region.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design enhances light emitting efficiency and reliability by eliminating shading and reducing the risk of PN junction structure damage during wire bonding, while maintaining high axial light and heat dissipation performance, suitable for vehicle displays with improved contrast.
Implementation Method 1
small-size vertical-type light emitting diode chip
Implementation Method 2
PN junction structure comprises a P-type semiconductor, an active layer and an N-type semiconductor
Implementation Method 3
good heat dissipation performance, the vertical-type light emitting diode is beneficial to color rendering operation under the high temperature condition
Data Source
AI summary
Disclosed is a small-size vertical-type light emitting diode chip with high luminous in a central region. A PN junction structure is arranged on a light emitting region base of an interface structure, the interface structure is provided with a P-type Ohmic contact area at the light emitting region base, a central area of the PN junction structure is above the P-type Ohmic contact area, an insulating layer is formed on an extending platform adjacent to the light emitting region base and extends to cover an N-type semiconductor of the PN junction structure to form a border covering region surrounding the N-type semiconductor, an N-type Ohmic contact electrode covers the border covering region, and an N-type electrode pad is arranged on the insulating layer and electrically connected with the N-type Ohmic contact electrode via a bridging connected metal layer.