Vertical Magnetic Chip Stacking for EMI-Resilient IC Packaging
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Solution Overview
Problem
Integrated circuit (IC) devices lack electromagnetic filtering and transmitting functionality, leading to increased board area consumption and potential semiconductor chip failure due to parasitic effects from discrete magnetics, especially at high frequencies.
Innovation Solution
The integration of magnetic chips and semiconductor chips within a multi-layer structure with a lead frame, where the magnetic chip is vertically bonded to the lead frame and the semiconductor chip is bonded on top of the magnetic chip, eliminating discrete magnetics and enhancing electromagnetic performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If discrete magnetics are used separately from IC devices, then electromagnetic functionality is provided, but board area consumption increases and parasitic effects impact performance
Solution Approach 1:
The patent combines the IC device and discrete magnetics into a single integrated package structure. The semiconductor chip is mounted on a lead frame that includes magnetic shielding materials and electromagnetic filtering components integrated within the same package, eliminating the need for separate discrete magnetics on the PC board and reducing parasitic inductance through closer proximity connections.
Solution Approach 2:
The patent transitions from a planar configuration where IC devices and discrete magnetics are mounted separately on the PC board to a three-dimensional integrated package structure. The multi-layer lead frame and stacked component arrangement utilize vertical space within the package, reducing the footprint on the PC board while maintaining electromagnetic functionality.
2Reliability
If discrete magnetics are used separately, then electromagnetic functionality is achieved, but parasitic inductance causes semiconductor chip failure at high frequencies
Solution Approach 1:
The patent extracts the harmful parasitic inductance effect by integrating the magnetic shielding and filtering components directly within the IC package. This allows the electromagnetic functionality to be provided at the source, eliminating the long trace inductance that occurs when discrete magnetics are connected via PCB traces, and removing the parasitic effects that cause high-frequency failures.
3Adaptability or versatility
If IC devices are mounted with discrete magnetics, then electromagnetic functionality is provided, but device complexity and board area increase
Solution Approach 1:
The patent creates a multi-functional integrated package where the lead frame serves multiple purposes: as the mechanical carrier for the semiconductor chip, as the electrical interconnection structure, and as the housing for electromagnetic filtering and shielding components. This single structure provides both the IC device functionality and the electromagnetic functionality, reducing overall system complexity despite the added capabilities.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces board area usage, improves RF and power management, minimizes electromagnetic interference, and enhances thermal balance, thereby increasing the reliability and signal integrity of the IC device.
Implementation Method 1
The magnetic chip in the first layer is disposed between the bonding pad of the lead frame and the semiconductor chip in the second layer
Implementation Method 2
vertically bonding a magnetic chip in a first layer of the IC device to a bonding pad of a lead frame, and vertically bonding at least one semiconductor chip in a second layer of the IC device to the magnetic chip in the first layer
Data Source
AI summary
Techniques for providing vertical integrations of semiconductor chips, magnetic chips, and lead frames. The techniques can include fabricating an integrated circuit (IC) device as a multi-layer IC structure that includes, within a sealed protective enclosure, a first layer including at least one magnetic chip, a second layer including at least one semiconductor chip or die, and a lead frame. The techniques can further include vertically bonding the magnetic chip in the first layer onto the topside of the lead frame, and vertically bonding the semiconductor chip or die in the second layer on top of the magnetic chip to form a multi-layer IC structure.