Vertical MBCFET Channel Stacking for Dense Semiconductor Integration
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Solution Overview
Problem
The challenge in manufacturing high-performance semiconductor devices with high integration is achieving fine patterns and spacings, particularly in fin field effect transistors (FinFETs) with three-dimensional channels, as existing technologies face limitations in device characteristics due to miniaturization of planar metal oxide semiconductor FETs (MOSFETs).
Innovation Solution
The semiconductor device incorporates a multi-bridge channel FET (MBCFET) structure with vertically spaced channel layers, a gate structure surrounding the channels, and source/drain regions on insulating structures, featuring distinct insulating layers and materials to enhance integration and reduce leakage currents.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If planar MOSFETs are miniaturized to increase integration density, then device integration increases, but device characteristics deteriorate
Solution Approach 1:
The patent transitions from planar (2D) MOSFET structure to three-dimensional FinFET structure by forming vertical fins on the substrate. This dimensional change allows for increased integration density while maintaining better device characteristics through enhanced gate control over the channel region.
Solution Approach 2:
The gate structure is designed to wrap around or surround the channel layers in a nested configuration, where the gate envelops the vertical fins from multiple sides. This nested gate architecture provides superior electrostatic control and enables continued scaling without sacrificing device performance.
2Reliability
If FinFET structure is implemented to improve device characteristics, then device performance improves, but manufacturing complexity increases
Solution Approach 1:
The manufacturing process is divided into distinct sequential steps: forming the fin structure, depositing gate material, forming source/drain regions, and adding insulating layers. This segmentation of complex 3D structure formation into manageable steps enables systematic fabrication of FinFET devices.
Solution Approach 2:
The fin structures are pre-formed on the substrate before gate and source/drain region formation. This preliminary creation of vertical channels establishes the three-dimensional architecture early in the process, simplifying subsequent steps and enabling better control over the overall device fabrication sequence.
3Object-generated harmful factors
If multi-layer insulating structures are added to reduce leakage currents, then leakage reduction improves, but device complexity increases
Solution Approach 1:
Different insulating materials are selectively placed in specific regions where leakage occurs most prominently, such as at the interfaces between channel layers and source/drain regions. This localized approach to insulation targets harmful leakage currents without requiring comprehensive insulation throughout the entire device structure.
Solution Approach 2:
Multiple insulating layers with different material properties are combined to create a composite insulation system. Each layer provides specific functions such as electrical isolation, mechanical support, or stress management, achieving effective leakage reduction through material composition rather than simple structural addition.
Data Source
AI summary
A semiconductor device may include first and second active regions on a substrate, first and second insulating structures on the first and second active regions, respectively, vertically stacked channel layers on each of the first and second insulating structures, first and second gate structures intersecting the first and second active regions, respectively, and surrounding the channel layers, first and second source/drain regions doped with different conductivity-type impurities, the first and second source/drain regions being on sides of the first and second gate structures, respectively, and contacting the channel layers, and at least a portion of each of the first and second insulating structures extending upwardly along a side surface of a corresponding one of the first and second source/drain regions.