Vertical Memory Cell Structure for High-Density 3D Arrays
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Solution Overview
Problem
The semiconductor industry faces challenges in scaling down integrated circuit (IC) manufacturing while maintaining complexity and efficiency, requiring advancements in IC processing and manufacturing to support increasingly complex and dense circuit designs.
Innovation Solution
A method of forming a memory device involves creating a stack structure with dielectric and conductive layers, patterning through holes, and filling recesses with data storage material, followed by the formation of channel and gate pillar structures, enabling the development of advanced memory arrays such as phase-change random access memory (PCRAM) and resistive random access memory (RRAM) devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If geometry size is decreased to increase functional density, then production efficiency and cost are improved, but processing complexity increases
Solution Approach 1:
The patent transitions from planar 2D memory structures to three-dimensional vertical stack structures, where memory cells are arranged in multiple tiers stacked vertically. This dimensional change allows increased storage density without proportionally increasing processing complexity, as the vertical stacking can be achieved through sequential deposition and patterning steps that build upon each other systematically.
Solution Approach 2:
The memory device is divided into multiple functional layers including word lines, bit lines, select lines, and storage elements arranged in distinct tiers. This segmentation allows each layer to be formed and processed independently through modular fabrication steps, making the complex 3D structure manageable through systematic sequential processing rather than requiring simultaneous complex patterning.
2Quantity of substance
If functional density is increased while scaling down, then more devices per chip area are achieved, but manufacturing complexity increases
Solution Approach 1:
By stacking memory cells vertically in multiple tiers along the depth direction, the patent achieves increased device quantity per chip area without requiring proportionally more complex manufacturing. The vertical stacking allows devices to be arranged in three dimensions rather than confined to a single plane, effectively multiplying storage capacity while using extensions of standard planar processing techniques applied sequentially.
Solution Approach 2:
The patent forms complete stacks of word lines, bit lines, and storage elements in predetermined patterns before final connection establishment. This preliminary structuring allows subsequent interconnection steps to proceed more simply, as the basic building blocks are already in place and properly positioned, reducing the complexity of establishing inter-device connections.
Data Source
AI summary
A memory device and method of forming the same are provided. The memory device includes a first memory cell disposed over a substrate. The first memory cell includes a transistor and a data storage structure coupled to the transistor. The transistor includes a gate pillar structure, a channel layer laterally wrapping around the gate pillar structure, a source electrode surrounding the channel layer, and a drain electrode surrounding the channel layer. The drain electrode is separated from the source electrode a dielectric layer therebetween. The data storage structure includes a data storage layer surrounding the channel layer and sandwiched between a first electrode and a second electrode. The drain electrode of the transistor and the first electrode of the data storage structure share a common conductive layer.