Vertical Memory Common Source Layout for Leakage-Free ACS Contact
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Solution Overview
Problem
Existing vertical memory device technologies face challenges in efficiently connecting array common source (ACS) structures to peripheral circuitry, leading to issues like word line to ACS leakage, large word line to ACS capacitance, and stress during processing, particularly due to ACS contact placement in gate line cut structures.
Innovation Solution
The implementation of a semiconductor device with a high conductive layer forming an array common source (ACS) that extends into a staircase region, allowing for flexible contact structure placement away from the array region, thereby reducing leakage and capacitance, and using a high conductive layer as an etch stop for forming contacts to the common source layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If contact structures are placed in gate line cut structures to connect ACS, then connectivity is achieved, but word line to ACS leakage and large capacitance occur
Solution Approach 1:
The contact structures are extracted from the gate line cut structures and relocated to the staircase region. This separation removes the harmful interaction between word lines and ACS contacts, eliminating leakage and capacitance issues while maintaining connectivity function.
Solution Approach 2:
The common source layer acts as an intermediary conductive path that extends from the array region through the staircase region to the contact structures. This intermediary structure enables connectivity without direct contact between word lines and ACS, resolving the leakage and capacitance problems.
2Reliability
If ACS contact is formed in gate line cut structure, then connection is established, but stress during processing occurs
Solution Approach 1:
The ACS contact formation is extracted from the gate line cut structure formation process. By placing contact structures in the staircase region rather than in gate line cut structures, the patent eliminates the stress issues that arise from forming contacts within the constrained gate line cut structure geometry during processing.
3Object-generated harmful factors
If contact structures are placed away from array region in staircase region, then leakage and capacitance are reduced, but manufacturing complexity increases
Solution Approach 1:
The staircase region serves multiple functions: it provides structural support for the vertical stack, creates access pathways to different levels, and now also serves as the location for ACS contact structures. This multi-functionality reduces manufacturing complexity by consolidating several functions into one region rather than requiring separate structures for each function.
4Adaptability or versatility
If common source layer extends over array and staircase region, then flexible contact placement is enabled, but device area increases
Solution Approach 1:
The common source layer extends in the lateral dimension across both array and staircase regions, utilizing the available horizontal space efficiently. This dimensional extension provides contact placement flexibility without requiring additional vertical stacking or increasing the core array area, as the extension occurs in the staircase region that would otherwise be unused space.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables efficient current distribution and reduces the core region size for the same memory capacity, minimizing word line to ACS leakage, eliminating word line to ACS capacitance, and alleviating stress-related issues, while allowing for flexible contact placement and reduced mask counts.
Implementation Method 1
The common source layer includes a metal silicon compound layer and a silicon layer. The metal silicon compound layer includes at least one of titanium (Ti), cobalt (Co), nickel (Ni), and platinum (Pt).
Implementation Method 2
forming a contact hole to the common source layer, using the etch stop layer as an etch stop, wherein the etch stop layer comprises the metal silicon compound layer
Data Source
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AI summary
Aspects of the disclosure provide a semiconductor device. The semiconductor device includes a stack of layers. The stack of layers includes a common source layer, gate layers and insulating layers disposed on a substrate. The gate layers and insulating layers are stacked alternatingly. Then, the semiconductor device includes an array of channel structures formed in an array region. The channel structure extends through the stack of layers and forms a stack of transistors in a series configuration. The channel structure includes a channel layer that is in contact with the common source layer. The common source layer extends over the array region and a staircase region. The semiconductor device includes a contact structure disposed in the staircase region. The contact structure forms a conductive connection with the common source layer.