Vertical Memory Device With Acute-Angle Lower Pattern
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Solution Overview
Problem
Current semiconductor devices face challenges in integrating word lines and dielectric layers effectively, particularly in NAND flash devices, where the integration of interlayer insulating layers and gate electrodes with semiconductor layers is not optimized, leading to inefficiencies in storage and reliability.
Innovation Solution
A semiconductor device design featuring a stack structure with interlayer insulating layers and word lines alternately stacked, including a semiconductor layer penetrating through the stack, a first dielectric layer with varying thickness portions, and a lower pattern closer to the substrate, which enhances the integration and reliability by forming a specific acute angle with the dielectric layer, improving cell distribution characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If interlayer insulating layers and gate electrodes are alternately stacked to form a stack structure, then integration density is improved, but manufacturing complexity increases
Solution Approach 1:
The stack structure is divided into multiple alternating layers of interlayer insulating layers and gate electrodes, with semiconductor layers positioned in openings between these stacked components. This segmentation allows for systematic integration of multiple functional elements in a vertical arrangement, improving integration density while maintaining manufacturability through modular construction
Solution Approach 2:
The patent transitions from planar device architecture to a vertical stack structure, utilizing the vertical dimension to accommodate multiple interlayer insulating layers and gate electrodes. This dimensional change enables higher integration density by stacking components vertically rather than arranging them horizontally, while the standardized repeating units facilitate manufacturing
2Reliability
If a first dielectric layer with varying thickness is introduced between the semiconductor layer and stack structure, then reliability is improved, but device complexity increases
Solution Approach 1:
The first dielectric layer is designed with non-uniform thickness, having a first thickness in a first region and a second thickness greater than the first thickness in a second region. This local variation in dielectric thickness provides enhanced reliability by offering different electrical characteristics and mechanical support in different areas of the device, while the localized complexity is managed through the structured regions
Solution Approach 2:
The dielectric layer's thickness parameter is deliberately varied across different regions of the device. The first thickness and second thickness represent different parameter values that optimize device performance and reliability in their respective regions, demonstrating parameter changes as an inventive principle to resolve the contradiction between reliability improvement and complexity increase
Data Source
AI summary
A semiconductor device includes a stack structure on a substrate, the stack structure including interlayer insulating layers and first gate electrodes alternately stacked on each other, a semiconductor layer in an opening penetrating through the stack structure, a first dielectric layer between the semiconductor layer and the stack structure, and a lower pattern closer to the substrate than to the first gate electrodes in the stack structure, the lower pattern including a first surface facing the first dielectric layer, and a second surface facing the stack structure, the second surface defining an acute angle with the first surface, wherein the first dielectric layer includes a first portion facing the stack structure, and a second portion facing the first surface of the lower pattern, the second portion having a thickness greater than a thickness of the first portion.