Vertical Memory Bit Line Air Gap Reduces Parasitic Capacitance
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Solution Overview
Problem
In three-dimensional semiconductor devices, such as vertical NAND strings, the capacitive coupling between bit lines and contact via structures contributes to significant parasitic capacitance, leading to increased RC delay, which is not effectively reduced by existing technologies.
Innovation Solution
The formation of a low dielectric constant dielectric material, such as a vacuum cavity or air cavity, over the contact via structures to minimize parasitic capacitance, achieved by depositing a non-conformal dielectric material that laterally surrounds the contact pillars and forms a contiguous volume with a dielectric constant less than 3.9.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional dielectric materials with higher dielectric constants are used in contact via structures, then the insulating capability is improved, but parasitic capacitance increases leading to increased RC delay
Solution Approach 1:
The patent changes the dielectric constant parameter of the material surrounding the contact pillars from conventional values (≥3.9) to low-k values (<3.9). This parameter change reduces parasitic capacitance between bit lines and contact via structures, thereby reducing RC delay and improving signal propagation speed while maintaining adequate insulating capability through the specific low-k material selection and structural design.
2Loss of time
If the dielectric constant is reduced to minimize parasitic capacitance, then RC delay is reduced, but the insulating capability may be compromised
Solution Approach 1:
The patent employs composite material structures including low-k dielectric materials combined with specific contact pillar materials and interface layers. The composite structure maintains insulating capability through the combined properties of different materials while achieving reduced parasitic capacitance through the low-k material's inherent properties. The composite approach allows optimization of both electrical insulation and capacitance reduction.
3Loss of time
If non-conformal dielectric deposition is used to surround contact pillars, then parasitic capacitance is reduced, but manufacturing complexity increases
Solution Approach 1:
The patent applies preliminary action by forming the low-k dielectric material in a non-conformal manner that selectively surrounds the contact pillars before subsequent processing steps. This preliminary deposition pattern is designed to optimize parasitic capacitance reduction while being compatible with standard semiconductor manufacturing processes, thereby managing complexity through careful process sequencing and material selection.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces parasitic capacitance and RC delay, enhancing the operational speed of the semiconductor devices by creating a low-k dielectric environment around the contact pillars and bit lines.
Implementation Method 1
the capacitive coupling between bit lines and contact via structures contributes to significant parasitic capacitance, leading to increased RC delay
Implementation Method 2
achieved by depositing a non-conformal dielectric material that laterally surrounds the contact pillars
Data Source
AI summary
A structure includes a three-dimensional semiconductor device including a plurality of unit device structures located over a substrate. Each of the unit device structures includes a semiconductor channel including at least a portion extending vertically along a direction perpendicular to a top surface of the substrate, and a drain region contacting a top end of the semiconductor channel. The structure also includes a combination of a plurality of contact pillars and a contiguous volume that laterally surrounds the plurality of contact pillars. The plurality of contact pillars is in contact with the drain regions, and the contiguous volume has a dielectric constant less than 3.9.