Vertical Memory Air-Gap Structure for Parasitic Capacitance Control
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Solution Overview
Problem
High integration density in semiconductor dies leads to reduced reliability due to increased parasitic capacitance, which affects device performance and power consumption.
Innovation Solution
A vertical memory structure is developed with air gaps between conductive features, specifically between gate electrodes and a common source/drain line, to reduce parasitic capacitance, comprising a semiconductor stack, contact plug, and gate electrodes, where the contact plug has a varying width and includes a barrier layer with aluminum fluoride and zinc oxide, and air gap structures are formed to separate these features electrically.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If high integration density is implemented in semiconductor dies, then device functionality and capacity are improved, but parasitic capacitance increases leading to reduced reliability
Solution Approach 1:
An air gap structure is introduced as an intermediary between the common source/drain line and gate electrodes. This air gap acts as a mediator that reduces parasitic capacitance coupling between these conductive features while allowing them to remain in close proximity for high integration density. The air gap structure includes a first air gap between the common source/drain line and first gate electrode, and a second air gap between the common source/drain line and second gate electrode, effectively decoupling the capacitive interaction.
2Productivity
If conductive features are placed closer together to increase integration, then device capacity is improved, but parasitic capacitance between features increases
Solution Approach 1:
The air gap structure serves as a physical intermediary that reduces parasitic capacitance between the common source/drain line and gate electrodes. By introducing this low-dielectric constant region (air) between the conductive features, the capacitive coupling is minimized while maintaining spatial proximity for high integration. The structure includes first and second air gaps positioned at different locations to address parasitic capacitance from multiple gate electrode interactions.
Solution Approach 2:
The dielectric parameter is changed by replacing traditional solid dielectric material with air (or vacuum) in the gap regions between conductive features. Since air has a much lower dielectric constant (~1.0) compared to conventional dielectric materials (typically 3.9 for SiO2 and higher for advanced dielectrics), this parameter change dramatically reduces parasitic capacitance while allowing the conductive features to remain closely spaced for high integration density.
Data Source
AI summary
The present disclosure provides a vertical memory structure including a semiconductor stack, a contact plug, gate electrodes and air gap structures. The semiconductor stack includes a lower semiconductor pattern structure filling a recess on a substrate and protruding from an upper surface of the substrate in a first direction substantially perpendicular to the upper surface of the substrate. The contact plug is disposed over the lower semiconductor pattern structure. The contact plug includes a lower portion and a middle portion over the lower portion. A width of the middle portion is less than a width of the lower portion. The gate electrodes are surrounding a sidewall of the semiconductor stack. The air gap structures are disposed at outer sides of the plurality of gate electrode respectively.