Vertical Semiconductor Memory Devices with Air Gap Insulation
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Solution Overview
Problem
Semiconductor memory devices face challenges in increasing dielectric breakdown voltage and reducing parasitic capacitance to meet the demands of higher integration densities and data throughput in smaller electronic devices.
Innovation Solution
The semiconductor memory device employs a vertical structure with gate electrodes separated by air gaps, a gate dielectric layer comprising tunneling, charge storage, and barrier insulating layers, and substrate contact electrodes extending vertically to enhance dielectric breakdown voltage and reduce parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional planar structure is used, then manufacturing is simpler, but integration density is limited
Solution Approach 1:
The patent transitions from a planar two-dimensional structure to a vertical three-dimensional structure by stacking memory cell strings, transistors, and interconnect layers vertically. This dimensional change enables significantly higher integration density within the same footprint area, as memory cells are arranged in multiple tiers rather than a single plane.
Solution Approach 2:
The patent implements nested structures where gate electrodes are wrapped around semiconductor pillars, and multiple functional layers are stacked within each other vertically. The gate dielectric layer is positioned between the gate electrode and semiconductor region, creating a nested configuration that maximizes space utilization and integration density.
2Quantity of substance
If gate electrodes are placed close together, then integration density increases, but parasitic capacitance increases
Solution Approach 1:
The patent introduces gate dielectric layers as intermediary materials positioned between adjacent gate electrodes and between the gate electrode and semiconductor region. These dielectric layers act as electrical insulators that reduce parasitic capacitance coupling while allowing the gate electrodes to remain in close proximity for high integration density.
Solution Approach 2:
The patent applies different dielectric materials with varying properties at different locations: high-k dielectric materials are used in specific regions to optimize capacitance characteristics, while air gaps or low-k materials are used in other regions to minimize parasitic capacitance. This localized differentiation allows simultaneous optimization of density and electrical performance.
3Quantity of substance
If dielectric layer thickness is reduced to increase density, then integration density increases, but dielectric breakdown voltage decreases
Solution Approach 1:
The patent employs composite dielectric structures consisting of multiple layers with different properties: tunneling insulating layers, charge storage layers, and barrier insulating layers are stacked sequentially. This composite approach allows thin overall thickness for high density while maintaining high breakdown voltage through the combined strength of individual layers, particularly the high-k barrier layer.
Solution Approach 2:
The patent changes the dielectric constant parameter by using high-k dielectric materials in the barrier insulating layer and charge storage layer. This parameter change allows the dielectric layer to be physically thinner (increasing density) while the high-k material provides equivalent or superior electrical insulation and breakdown voltage characteristics compared to thicker low-k materials.
4Quantity of substance
If vertical structure is implemented, then integration density increases, but manufacturing complexity increases
Solution Approach 1:
The patent divides the manufacturing process into distinct sequential stages: forming semiconductor pillars, depositing gate dielectric layers, forming gate electrodes, creating interconnect structures, and adding control circuits. Each stage is independently optimized and can be performed using standard semiconductor fabrication techniques, making the complex vertical structure manufacturable through modular process segmentation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration improves the reliability and operational stability of semiconductor memory devices by increasing dielectric breakdown voltage and reducing parasitic capacitance, enabling higher integration densities and data throughput.
Implementation Method 1
a gate dielectric layer comprising tunneling, charge storage, and barrier insulating layers
Implementation Method 2
gate dielectric layer disposed between the semiconductor region and the plurality of gate electrodes
Implementation Method 3
an insulating region formed as an air gap between the substrate contact electrode and at least one of the plurality of gate electrodes
Data Source
AI summary
A semiconductor memory device includes: a semiconductor region extending vertically from a first region of a substrate; a plurality of gate electrodes disposed on the first region of the substrate in a vertical direction, but separated from each other along a sidewall of the semiconductor region; a gate dielectric layer disposed between the semiconductor region and the plurality of gate electrodes; a substrate contact electrode extending vertically from the impurity-doped second region of the substrate; and an insulating region formed as an air gap between the substrate contact electrode and at least one of the plurality of gate electrodes.