Vertical Memory Air Gap Design Prevents Metal Infiltration

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Solution Overview

Problem

During the fabrication of VNAND flash memory devices, voids can be generated in polysilicon layers if they do not completely fill gaps, leading to potential degradation of the memory device characteristics.

Innovation Solution

A vertical memory device design that includes a channel connecting pattern with an air gap, where the air gap is not formed adjacent to the common source line, preventing metal infiltration and maintaining device integrity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If polysilicon layers are used to fill gaps between channels, then channel connectivity is improved, but voids may be generated leading to device degradation

Engineering Contradiction:
Improvechannel connectivityVSAvoidgap filling completeness
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The patent removes the problematic polysilicon material from the gap region and replaces it with an air gap structure. This extraction eliminates the void formation issue while maintaining the electrical isolation function, as the air gap naturally prevents metal infiltration without requiring complete polysilicon filling.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent introduces an air gap (inert environment) between the channels and metal lines to prevent metal infiltration. The air gap acts as a barrier that isolates the metal from the channel region, eliminating the need for complete polysilicon filling and preventing device degradation.

Inventive Principle:
Principle #39Inert atmosphere (Inert environment)

2Reliability

If air gaps are introduced to prevent metal infiltration, then device reliability is improved, but manufacturing complexity increases

Engineering Contradiction:
Improvemetal infiltration preventionVSAvoidstructure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent segments the gap-filling process into distinct regions: air gap regions where metal infiltration must be prevented, and polysilicon-filled regions where connectivity is required. This segmentation allows the air gap to be strategically placed only where needed for metal infiltration prevention, rather than throughout the entire structure.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent applies different material properties to different locations: air gaps are created specifically in regions adjacent to metal lines where infiltration prevention is critical, while other regions maintain polysilicon filling for electrical connectivity. This local differentiation optimizes both reliability and manufacturing feasibility.

Inventive Principle:
Principle #3Local quality

3Reliability

If channel connecting patterns are formed to connect channels, then electrical connectivity is improved, but metal infiltration risk increases

Engineering Contradiction:
Improvechannel connectivityVSAvoidmetal infiltration
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The patent introduces an air gap as an intermediary barrier between the channel connecting pattern and the metal lines. This air gap mediates the interaction by providing electrical isolation and preventing direct contact between metal and the channel region, thereby eliminating infiltration risk while allowing the connecting pattern to maintain connectivity.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS11521987B2Vertical memory devices
Publication Date: 2022.12.06 SAMSUNG ELECTRONICS CO LTD
  • US11521987B2 patent drawing
  • US11521987B2 patent drawing
  • US11521987B2 patent drawing

AI summary

A vertical memory device may include a channel connecting pattern on a substrate, gate electrodes spaced apart from each other in a first direction on the channel connecting pattern, and a channel extending in the first direction through the gate electrodes and the channel connecting pattern. Each of the electrodes may extend in a second direction substantially parallel to an upper surface of the substrate, and the first direction may be substantially perpendicular to the upper surface of the substrate. An end portion of the channel connecting pattern in a third direction substantially parallel to the upper surface of the substrate and substantially perpendicular to the second direction may have an upper surface higher than an upper surface of other portions of the channel connecting pattern except for a portion thereof adjacent the channel.