Vertical Memory Air-Gap Structure for Lower Parasitic Capacitance
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Solution Overview
Problem
High integration density in semiconductor dies leads to reduced reliability due to increased parasitic capacitance and RC delay, which affects device performance and power consumption.
Innovation Solution
A vertical memory structure is developed with air gaps between conductive features, such as gate electrodes and the common source/drain line, to reduce parasitic capacitance. This structure includes a semiconductor stack, contact plugs with specific width transitions, and air gap structures formed by energy removable blocks transformed during a heat treatment process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If high integration density is implemented in semiconductor dies, then device functionality and capacity are improved, but parasitic capacitance and RC delay increase leading to reduced reliability
Solution Approach 1:
Air gap structures are introduced as intermediary elements between adjacent gate electrodes and between conductive features. These air gaps act as dielectric mediators with lower permittivity than traditional solid dielectrics, thereby reducing parasitic capacitance coupling while maintaining the high integration density architecture. The air gaps are formed by removing sacrificial blocks and serve as spacing structures that electrically isolate conductive elements.
Solution Approach 2:
The patent utilizes air-filled porous structures (air gaps) between conductive features instead of solid dielectric materials. These porous air gap structures reduce the effective permittivity in the inter-conductive region, thereby reducing parasitic capacitance and RC delay while preserving the compact high-density vertical memory architecture.
2Quantity of substance
If high integration density is implemented, then device capacity is improved, but power consumption increases due to increased parasitic capacitance
Solution Approach 1:
Air gap structures serve as intermediary dielectric elements between adjacent gate electrodes and conductive features. By using air (lower permittivity) instead of solid dielectric materials, the parasitic capacitance is reduced, which directly decreases the energy required for charging and discharging operations, thereby reducing power consumption in high-density memory devices.
3Ease of manufacture
If conventional solid dielectric structures are used between conductive features, then manufacturing simplicity is maintained, but parasitic capacitance is high affecting device performance
Solution Approach 1:
The patent applies the extraction principle by removing sacrificial blocks (silicon nitride or silicon oxide) from specific regions to create air gap structures. This extraction of material creates void spaces filled with air, which have lower permittivity than solid dielectrics. The process integrates seamlessly with existing semiconductor manufacturing steps including sacrificial layer deposition, patterning, and removal, thereby maintaining manufacturing simplicity while reducing parasitic capacitance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The introduction of air gaps effectively reduces parasitic capacitance, thereby improving device performance by decreasing power consumption and RC delay, and increasing the yield rate of semiconductor devices.
Implementation Method 1
air gaps between conductive features, such as gate electrodes and the common source/drain line, to reduce parasitic capacitance
Implementation Method 2
air gap structures formed by energy removable blocks transformed during a heat treatment process
Data Source
AI summary
The present disclosure provides a vertical memory structure including a semiconductor stack, a contact plug, gate electrodes and air gap structures. The semiconductor stack includes a lower semiconductor pattern structure filling a recess on a substrate and protruding from an upper surface of the substrate in a first direction substantially perpendicular to the upper surface of the substrate. The contact plug is disposed over the lower semiconductor patterns structure. The contact plug includes a lower portion and a middle portion over the lower portion. A width of the middle portion is less than a width of the lower portion. The gate electrodes are surrounding a sidewall of the semiconductor stack. The air gap structures are disposed at outer sides of the plurality of gate electrode respectively.