Vertical Memory Device Anti-Coupling Structure
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Solution Overview
Problem
As vertical NAND flash memory devices are downsized with increasing stack density, electron diffusion and cross-talk between neighboring cells become more frequent, leading to reliability issues due to insufficient trap density and variable memory window sizes.
Innovation Solution
The solution involves increasing the trap density by alternating charge trap patterns and dielectric inter-cell patterns, and incorporating an anti-coupling structure with a lower dielectric constant in the inter-cell region to reduce electron diffusion and cross-talk, while maintaining a higher trap density in cell regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the vertical gap distance between neighboring stack cells is reduced to increase stack density, then the memory capacity is improved, but electron diffusion and cross talk between cells increase
Solution Approach 1:
The charge trap layer is segmented into cell regions and inter-cell regions with different thicknesses. The inter-cell region has a reduced thickness (first thickness) compared to the cell region (second thickness), creating distinct functional zones that prevent electron diffusion while maintaining storage capacity.
Solution Approach 2:
Different regions of the charge trap layer are given different local properties: the cell region maintains high trap density for charge storage, while the inter-cell region has reduced thickness to act as an electron barrier. This local differentiation resolves the contradiction between density and reliability.
2Length of moving object
If the charge trap pattern height is decreased due to reduced vertical gap distance, then the device size is reduced, but the trap density becomes insufficient and memory window size becomes variable
Solution Approach 1:
The charge trap layer exhibits local quality variation with different thicknesses in cell versus inter-cell regions. This allows the overall device size to be reduced while maintaining sufficient trap density in cell regions for stable memory window operation.
Solution Approach 2:
Instead of uniformly reducing charge trap layer thickness in all dimensions, the invention varies thickness selectively in the vertical dimension at different horizontal positions (cell vs inter-cell regions), maintaining functionality while enabling downsizing.
3Quantity of substance
If the vertical gap distance between cells is reduced, then integration density is improved, but coupling between neighboring cells increases
Solution Approach 1:
The charge trap layer is divided into segments with different thicknesses, creating distinct cell and inter-cell regions. This segmentation reduces coupling between neighboring cells by introducing thinner barrier sections while maintaining high integration density through vertical stacking.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances the reliability and stability of the vertical memory device by minimizing electron diffusion and cross-talk, maintaining consistent programming and erasing voltages, and preventing electron diffusion between neighboring cells, even at higher integration densities.
Implementation Method 1
The anti-coupling structure may have a dielectric constant smaller than that of the charge trap pattern
Data Source
AI summary
Disclosed are vertical memory devices and methods of manufacturing the same. The vertical memory device may include includes a substrate, a gate stack structure and channel structure on the substrate, and a charge trap structure between the gate stack structure and the channel structure. The gate stack structure includes conductive structures and insulation interlayer structures that are alternately stacked on each other in a vertical direction on the substrate such that cell regions and inter-cell regions are alternately arranged in the vertical direction. The channel structure penetrates through the gate stack structure in the vertical direction. The charge trap structure and the conductive structures define memory cells at the cell regions. The charge structure is configured to selectively store charges. The charge trap structure includes an anti-coupling structure in the inter-cell region for reducing a coupling between neighboring memory cells adjacent to each other in the vertical direction.