Vertical Memory Cell Layout With Anti-Fuse Redundancy Repair
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Solution Overview
Problem
Discarding semiconductor memory devices due to defects in only some unit cells is inefficient, as they can be restored by replacing failed cells with redundancy cells to improve yield.
Innovation Solution
A semiconductor memory device design incorporating vertical channel transistors and anti-fuse gate electrodes allows for the replacement of defective cells with redundancy cells, using anti-fuse circuits to reprogram the device, thereby improving integration and reducing the horizontal area occupied by these circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If semiconductor memory devices are discarded due to defects in some unit cells, then manufacturing simplicity is maintained, but product yield deteriorates
Solution Approach 1:
Redundancy cells are pre-configured in the memory device during manufacturing, ready to replace defective unit cells. This preliminary preparation enables yield improvement without adding complex repair mechanisms, as the replacement capability is built-in from the start
Solution Approach 2:
The gate insulating layer thickness is changed to create anti-fuse structures with specific electrical characteristics. By controlling the thickness parameter, the device transitions from normal operation mode to anti-fuse programming mode, enabling defective cell replacement through electrical reconfiguration rather than physical repair
2Productivity
If anti-fuse circuits are used to replace defective cells, then product yield is improved, but horizontal area increases
Solution Approach 1:
The patent transitions from two-dimensional planar transistors to three-dimensional vertical channel transistors. This dimensional change allows the anti-fuse circuits and redundancy cells to be stacked vertically, significantly reducing the horizontal area required for yield improvement mechanisms while maintaining full functionality
3Area of stationary object
If vertical channel transistors are used, then integration is improved and horizontal area is reduced, but manufacturing precision requirements increase
Solution Approach 1:
The patent incorporates back gate lines and back gate electrodes that can compensate for manufacturing variations in vertical channel transistors. By adjusting the back gate voltage, deviations in threshold voltage and electrical characteristics caused by manufacturing imprecision can be corrected, ensuring reliable device performance
Solution Approach 2:
The thickness of the gate insulating layer is precisely controlled to enable anti-fuse formation. By adjusting this critical parameter, the device can transition between normal transistor operation and anti-fuse programming modes, providing a manufacturable solution that balances precision requirements with functional flexibility
Data Source
AI summary
A semiconductor memory device includes a first structure on a substrate and including core regions and a first peripheral circuit region, and a second structure on the first structure and including cell array regions and a second peripheral circuit region. The second structure includes a first active pattern in each of the cell array regions and perpendicular to an upper surface of the first structure, a word line adjacent to one side of the first active pattern and extending in a first direction parallel to the upper surface of the first structure, a bit line in contact with a lower surface of the first active pattern and extending in a second direction intersecting the first direction, a second active pattern in the second peripheral circuit region and perpendicular to the upper surface of the first structure, and an anti-fuse gate electrode on one side of the second active pattern.