Vertical Memory Array Design for High Density
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Solution Overview
Problem
Conventional flash memory devices face limitations in increasing density and reducing size and cost due to short channel effects from process scaling, which also affects device performance, and existing multi-level charge techniques are not sufficient to meet the growing demands of new applications.
Innovation Solution
The development of a memory array with vertical memory cells that store 4 bits per cell, utilizing multi-level charge techniques and eliminating the need for isolation layers between cells, allowing for a compact and high-density design with adjustable channel length to enhance device performance without increasing size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If process scaling is used to reduce cell size and increase density, then memory density increases and cost per bit decreases, but short channel effects increase causing hot carrier damage and punch through that degrade device performance
Solution Approach 1:
The patent transitions from planar transistor geometry to vertical transistor geometry, changing the dimensional orientation of the channel. This vertical configuration allows the channel to extend perpendicular to the substrate surface, enabling longer channel lengths without increasing the lateral footprint of the memory cell. The vertical structure maintains scalability while avoiding short channel effects by providing better gate control over the extended channel region.
Solution Approach 2:
The patent changes the geometric parameters of the transistor structure by inverting the traditional planar configuration into a vertical architecture. This parameter change allows independent optimization of channel length for performance while maintaining compact cell area for density. The vertical structure enables longer channels without proportionally increasing the area occupied by each cell, thus resolving the contradiction between density and performance.
2Reliability
If channel length is increased to reduce junction capacitance and improve device performance, then device performance improves, but cell size increases limiting further scaling
Solution Approach 1:
By transitioning to vertical transistor geometry, the channel extends in the vertical dimension rather than the lateral dimension. This allows the channel length to increase for better performance without increasing the lateral area of the cell. The vertical structure stacks the channel above the substrate, utilizing the third dimension to accommodate longer channels while maintaining compact footprints.
Solution Approach 2:
The vertical transistor structure nests the channel within a compact footprint by extending it vertically above the substrate rather than laterally across the substrate surface. This nesting approach allows long channels to be contained within a small lateral area, similar to how a long object can be nested vertically within a compact base area.
Data Source
AI summary
A memory array comprising vertical memory cells does not require any isolation layers between cells. Thus, a very compact, high density memory array can be achieved. Each memory cell in the memory array is configured to store 4 bits of data per cell. Multi level charge techniques can be used to increase the number of bit per cell and achieve further increased density for the memory array.