Vertical Memory Array Gate-Last Formation
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Solution Overview
Problem
Current memory array technologies face challenges in efficiently forming vertically-stacked memory cells with precise control over gate structures and charge-blocking regions, which affects the reliability and retention time of non-volatile memory cells.
Innovation Solution
The method involves a 'gate-last' or 'replacement-gate' processing approach, where vertically-alternating insulative and wordline tiers are formed with sacrificial materials, followed by selective deposition and etching to create charge-blocking and charge-storage regions, enabling the formation of memory cells with precise control over gate structures and charge-blocking functions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional memory array formation methods are used, then manufacturing process is simpler, but manufacturing precision and control over gate structures and charge-blocking regions deteriorates
Solution Approach 1:
The patent applies preliminary action by forming sacrificial materials (first and second sacrificial materials) in advance during the stack formation process, before the actual gate and charge-blocking regions are created. These pre-positioned sacrificial materials guide subsequent selective deposition and etching steps, enabling precise control over the final gate structures and charge-blocking regions without requiring complex direct patterning at those stages.
Solution Approach 2:
The patent uses sacrificial materials as intermediary elements that facilitate the formation of precise gate structures and charge-blocking regions. These intermediaries are deposited selectively on specific tiers of the stack, then removed to create the desired structures. The sacrificial materials act as temporary mediators that enable precise spatial control during manufacturing, which is then removed after serving its purpose.
2Manufacturing precision
If gate-last or replacement-gate processing is used, then control over charge-blocking and charge-storage regions improves, but manufacturing process complexity increases
Solution Approach 1:
The patent segments the memory array formation process into distinct stages with different sacrificial materials for different functions. First sacrificial materials are used for one purpose (forming initial structures), then second sacrificial materials are used for another purpose (forming charge-blocking regions). This segmentation allows each material and process step to be optimized independently, improving control over charge-blocking and charge-storage regions while organizing the complexity into manageable segments.
Solution Approach 2:
The patent applies local quality by using different sacrificial materials with different properties at different locations and tiers of the stack. Each sacrificial material is selectively deposited on specific tiers where its particular properties are needed, enabling precise local control over the formation of gate structures and charge-blocking regions without requiring uniform processing across the entire structure.
Data Source
AI summary
A memory array comprises a vertical stack comprising alternating insulative tiers and wordline tiers. The wordline tiers comprise gate regions of individual memory cells. The gate regions individually comprise part of a wordline in individual of the wordline tiers. Channel material extends elevationally through the insulative tiers and the wordline tiers. The individual memory cells comprise a memory structure laterally between the gate region and the channel material. Individual of the wordlines comprise laterally-outer longitudinal-edge portions and a respective laterally-inner portion laterally adjacent individual of the laterally-outer longitudinal-edge portions. The individual laterally-outer longitudinal-edge portions project upwardly and downwardly relative to its laterally-adjacent laterally-inner portion. Methods are disclosed.


