Vertical Memory Cell Array Layout for Lower Parasitic Capacitance
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Solution Overview
Problem
The miniaturization of memory cells in semiconductor devices leads to increased parasitic capacitance, making it difficult to enhance memory cell density due to structural limitations.
Innovation Solution
The implementation of highly integrated vertical memory cell arrays with multi-layer level sub-word lines and vertically stacked sub-word line driver circuits, which include interconnections that electrically connect the sub-word lines to the drivers and position the drivers underneath the ends of the sub-word lines, allowing for reduced parasitic capacitance and increased memory cell density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cell size is miniaturized to increase net die, then memory cell density is improved, but parasitic capacitance increases
Solution Approach 1:
The patent transitions from planar memory cell arrangement to three-dimensional vertical stacking. Memory cells are arranged in multiple layers along the vertical direction, with bit lines and plate lines extending in the vertical dimension. This dimensional change allows increased storage capacity without proportionally increasing parasitic capacitance, as the vertical arrangement reduces overlapping area between conductive elements compared to dense planar layouts.
Solution Approach 2:
The memory cell array is divided into multiple independently controllable blocks, each with its own bit lines and plate lines. This segmentation allows selective activation of specific memory cell groups, reducing the total parasitic capacitance that must be charged/discharged during operations. The bit lines are segmented into multiple vertical lines, and plate lines are divided into separate groups that can be independently controlled.
2Area of stationary object
If memory cell size is decreased, then net die is increased, but structural limitations prevent further density enhancement
Solution Approach 1:
The patent overcomes planar structural limitations by implementing vertical three-dimensional memory cell structures. Memory cells stack multiple layers in the vertical direction, with conductive lines extending vertically through the structure. This approach dramatically increases storage density within the same footprint area, effectively removing the constraint of planar layout limitations and enabling continued scaling without further miniaturization of individual cell components.
Data Source
AI summary
A memory device includes: a first memory cell mat that includes first multi-layer level sub word lines positioned over a substrate; a second memory cell mat that is laterally spaced apart from the first memory cell mat and includes second multi-layer level sub word lines; a first sub word line driver circuit that is positioned underneath the first memory cell mat; and a second sub word line driver circuit that is positioned underneath the second memory cell mat, wherein the first sub word line driver circuit is positioned underneath ends of the first multi-layer level sub word lines, and the second sub word line driver circuit is positioned underneath ends of the second multi-layer level sub word lines.