Vertical Memory Stack Layout With Barrier Patterns for Higher Density

The patent transitions from planar two-dimensional memory cell arrangement to three-dimensional vertical stacking, where multiple layers of memory cells are stacked in the vertical direction. This dimensional change enables significantly increased storage capacity by utilizing the vertical space above the substrate, allowing memory cells to be arranged in multiple levels rather than a single plane.

The three-dimensional memory structure is divided into multiple functional layers including interlayer insulating layers, horizontal layers, vertical memory structures, barrier structures, and supporter patterns. Each layer performs a specific function and is systematically organized, which manages the complexity by creating a modular architecture that can be manufactured using standardized processes.

Supporter patterns are formed in advance before the vertical memory structures and barrier structures are created. These supporter patterns serve as pre-established reference structures that define the positions and orientations of subsequent layers, ensuring that vertical structures are aligned correctly and reducing the precision requirements during later manufacturing steps.

Interlayer insulating layers are introduced as intermediary structures between the substrate and the vertical memory structures. These insulating layers provide a standardized interface and spacing reference, making it easier to position vertical memory structures and barrier structures with consistent precision across the device.