Vertical Memory Strings with Individually Biasable Channels
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Solution Overview
Problem
Current NAND memory devices face challenges in increasing memory density while maintaining reliability, as reducing feature size increases the risk of tunnel dielectric failure and charge leakage, and stacking layers becomes costly and complex.
Innovation Solution
The implementation of a vertical memory array structure where each memory cell in a NAND string shares a common control gate but has individually biasable channel regions, formed using an alternating structure of semiconductor materials with different conductivity types, allowing for selective activation of memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If feature size is reduced to increase memory density, then memory density is improved, but the risk of tunnel dielectric failure and charge leakage increases
Solution Approach 1:
The patent divides the memory array into multiple independently biasable channel regions within vertical NAND strings. Each channel region can be selectively activated or deactivated, allowing the system to segment the memory operation into smaller, more reliable units. This segmentation reduces the stress on any single tunnel dielectric layer while maintaining high overall memory density through the vertical architecture.
Solution Approach 2:
The patent transitions from planar memory architecture to vertical NAND strings, moving the memory structure into the third dimension. This vertical stacking allows memory density to increase without proportionally reducing feature size, thereby maintaining tunnel dielectric thickness and reliability while achieving higher memory capacity per unit area.
2Quantity of substance
If multiple layers of memory arrays are stacked to increase density, then memory density is improved, but manufacturing complexity and cost increase
Solution Approach 1:
The patent merges multiple memory cells into shared NAND strings with common control gates. Instead of fully independent memory cell structures, multiple cells share control gate electrodes and channel regions, reducing the number of discrete components that need to be manufactured and assembled. This merging approach simplifies the manufacturing process while maintaining high memory density through vertical stacking.
Solution Approach 2:
The control gate structures serve multiple functions: they control multiple memory cells simultaneously, provide individual biasing capability for each channel region, and enable selective activation of specific memory cells within a NAND string. This multi-functionality reduces the need for additional specialized structures, simplifying manufacturing while achieving high memory density.
3Device complexity
If memory cells share a common control gate to simplify structure, then device complexity is reduced, but selective access to individual memory cells becomes difficult
Solution Approach 1:
The patent applies local quality by providing individual biasing capability to each channel region associated with a common control gate. While the control gate structure itself is shared and simplified, each channel region can receive distinct voltage biases, enabling selective activation of specific memory cells. This local differentiation in biasing conditions allows precise cell selection without complicating the overall control gate architecture.
Solution Approach 2:
The patent introduces dynamic biasing control where channel regions can be individually activated or deactivated through time-varying voltage applications. The selective access is achieved by dynamically adjusting the bias conditions of different channel regions during read and write operations, allowing flexible and precise memory cell selection while maintaining a simplified static control gate structure.
Data Source
AI summary
Multi-semiconductor vertical memory strings, strings of memory cells having individually biasable channel regions, arrays incorporating such strings and methods for forming and accessing such strings are provided. For example non-volatile memory devices are disclosed that utilize NAND strings of serially-connected non-volatile memory cells. One such string can include two or more serially connected non-volatile memory cells each having a channel region. Each memory cell of the two or more serially connected non-volatile memory cells shares a common control gate and each memory cell of the two or more serially connected non-volatile memory cells is configured to receive an individual bias to its channel region.