Vertical Memory Device Bit Line Pitch Optimization
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Solution Overview
Problem
Integrated circuit devices face challenges in achieving high integration and minimizing chip size due to complex operation circuits and wiring structures, particularly in memory devices where the increase in word lines leads to undesirable chip size expansion and reduced integration.
Innovation Solution
The design incorporates a vertical memory device structure with optimized bit line and word line configurations, including linear and nonlinear channel structures, and variable pitch bit lines to maximize bit line density while minimizing dummy channels, thereby suppressing chip size growth and enhancing integration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of word lines stacked in the memory cell region increases to achieve higher capacity, then the memory capacity increases, but the chip size undesirably increases and integration degree deteriorates
Solution Approach 1:
The patent transitions from planar memory architecture to vertical memory architecture by stacking word lines in the vertical direction (Z-axis) rather than arranging them horizontally. This dimensional change allows multiple word lines to occupy the same footprint area, increasing memory capacity without proportionally increasing chip area. The vertical stacking enables NAND-type memory structure where channel structures extend vertically through multiple word lines.
Solution Approach 2:
The patent implements a nested structure where channel structures are vertically nested through multiple stacked word lines. The channel structures pass through successive word lines in the vertical direction, creating a compact nested arrangement that maximizes memory cell density within the available chip area while maintaining electrical connectivity through the stacked layers.
2Quantity of substance
If the number of word lines stacked in the memory cell region increases to achieve higher capacity, then the memory capacity increases, but the number of dummy channels increases and integration degree deteriorates
Solution Approach 1:
The patent applies different pitch configurations for bit lines in different regions of the memory cell area. The first pitch is used in the center region where memory cells are densely packed, while the second pitch is used in the edge region. This local differentiation optimizes the use of channel structures, reducing the need for dummy channels in edge regions while maintaining high density in the center region, thereby improving overall integration.
3Quantity of substance
If bit line density is maximized to improve integration, then the number of bit lines per area increases, but the wiring structure becomes more complex
Solution Approach 1:
The patent segments the bit line array into two distinct groups: first bit lines with a first pitch arranged in the center region, and second bit lines with a second pitch arranged in the edge region. This segmentation allows optimized wiring density in different areas, maximizing bit line count without uniformly increasing complexity across the entire structure. The segmented approach enables selective optimization of wiring routes.
Data Source
AI summary
Provided is an integrated circuit device including a plurality of word lines overlapping each other, in a vertical direction, on a substrate, a plurality of channel structures extending in the vertical direction through the plurality of word lines on an area of the substrate, a plurality of bit line contact pads on the plurality of channel structures, and a plurality of bit lines, wherein the plurality of bit lines include a plurality of first bit lines extending parallel to each other at a first pitch in a center region of the area, and a plurality of second bit lines extending at a second pitch in an edge region of the area, the second pitch being different from the first pitch.