Block Architecture for Vertical Memory Array Area Efficiency
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Solution Overview
Problem
Three-dimensional memory structures face inefficiencies in area utilization due to increasing proportions of socket regions relative to memory cells as the number of memory cells and layers increase, leading to high costs and limited size reduction.
Innovation Solution
The proposed solution involves optimizing the allocation of bit line and word line bits in three-dimensional memory structures, with a greater number of bit line bits than word line bits, and configuring the memory structure to minimize the area occupied by socket regions relative to the memory array, using a block architecture that includes multiple conductive lines and socket regions to efficiently connect memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of memory cells in the memory array is increased, then memory density is improved, but the area occupied by socket regions increases relative to the memory array area
Solution Approach 1:
The patent transitions from a two-dimensional memory array layout to a three-dimensional architecture by stacking multiple memory arrays vertically across multiple decks. This dimensional change allows memory cells to be arranged in three dimensions rather than just two, significantly increasing memory density without proportionally increasing the footprint area of socket regions. The bit lines extend vertically through multiple decks to access memory cells on different levels, effectively utilizing the vertical dimension to pack more memory cells into the same planar area.
2Quantity of substance
If the number of bit lines and word lines is increased, then memory array capacity is improved, but the area of socket regions becomes increasingly large
Solution Approach 1:
The patent merges multiple bit lines from different decks by extending them vertically so that a single bit line socket region can access memory cells across multiple decks. Instead of requiring separate socket regions for each deck's bit lines, the design combines access paths vertically, reducing the total socket region area. Word lines are similarly organized to share socket regions across decks, consolidating the interface area required for signal line access.
3Quantity of substance
If the number of decks or layers within the memory structure is increased, then memory density is improved, but the area of socket regions increases relative to the memory array area
Solution Approach 1:
The patent utilizes the vertical dimension by stacking multiple memory arrays across several decks, allowing memory cells to be arranged in three dimensions. This vertical stacking increases memory density without proportionally increasing the planar footprint of socket regions, as the additional decks are accessed through the same or shared socket regions via vertical bit line extensions.
Solution Approach 2:
The socket regions are designed to serve multiple decks simultaneously through shared access paths. Bit line socket regions and word line socket regions function as universal interfaces that can access memory cells across multiple decks, rather than requiring dedicated socket regions for each deck. This multi-functionality reduces the total socket region area required as the number of decks increases.
Data Source
AI summary
Three-dimensional memory structures that are configured to use area efficiently, and methods for providing three-dimensional memory structures that use area efficiently are provided. The vertical memory structure can include a number of bit line bits that is greater than a number of word line bits. In addition, the ratio of bit line bits to word line bits can be equal to a ratio of a first side a memory cell included in a memory array of the memory structure to a dimension of a second side of the memory cell.